73S8009R-IL/F Maxim Integrated Products, 73S8009R-IL/F Datasheet
73S8009R-IL/F
Specifications of 73S8009R-IL/F
Related parts for 73S8009R-IL/F
73S8009R-IL/F Summary of contents
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... Card presence and faults are reported to the host through an interrupt output. When the 73S8009R is ready to support a card with the selected voltage, a RDY signal informs the host it can initiate the card activation sequence. ...
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... ESD protection on the card interface • SO28 or QFN20 package VCC FAULT VPC FAULT vref bias currents 1.5MHz TEMP FAULT R-C SMART CARD I/O BUFFERS Pin numbers reference the SO28 package reference the QFN20 Package Figure 1: 73S8009R Block Diagram DS_8009R_056 ): VPC [9] 15 LDO REGULATOR 20 [12] ...
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... Smart Card Interface Requirements ........................................................................................ 9 2.4 Digital Signals Characteristics ............................................................................................... 11 2.5 DC Characteristics ................................................................................................................ 11 2.6 Voltage / Temperature Fault Detection Circuits ...................................................................... 12 3 Applications Information ............................................................................................................. 13 3.1 Example 73S8009R Schematics ........................................................................................... 13 3.2 System Controller Interface ................................................................................................... 14 3.3 Power Supply and Voltage Supervision ................................................................................. 14 3.4 Card Power Supply ............................................................................................................... 14 3.5 Over-temperature Monitor ..................................................................................................... 15 3.6 Activation and Deactivation Sequence ...
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... Data Sheet Figures Figure 1: 73S8009R Block Diagram ......................................................................................................... 2 Figure 2: 73S8009R 20-Pin QFN Pinout .................................................................................................. 5 Figure 3: 73S8009R 28-Pin SO Pinout ..................................................................................................... 5 Figure 4: Typical 73S8009R Application Schematic ............................................................................... 13 Figure 5: Activation Sequence ............................................................................................................... 15 Figure 6: Deactivation Sequence ........................................................................................................... 16 Figure 7: OFF Activity Outside and Inside a Card Session ..................................................................... 17 Figure 8: Power-down Operation ........................................................................................................... 17 Figure 9: CS Timing Definitions .............................................................................................................. 18 Figure 10: I/O and I/OUC State Diagram ...
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... DS_8009R_056 1 Pinout The 73S8009R is supplied as a 20-pin QFN package and as a 28-pin SO package. I/OUC CMDVCC% CMDVCC# RSTIN CLKIN Figure 2: 73S8009R 20-Pin QFN Pinout AUX1UC AUX2UC CMDVCC% CMDVCC# PWRDN Rev. 1 TERIDIAN 3 73S8009R 4 5 (Top View TEST1 OFF 25 4 I/OUC RSTIN 10 19 ...
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... GND 27 12 Microcontroller Interface OFF Table 1: 73S8009R Pin Definitions Type IO Card I/O: Data signal to/from card. Includes a pull-up resistor to V CC. IO AUX1: Auxiliary data signal to/from card. Includes a pull-up resistor to V CC. IO AUX2: Auxiliary data signal to/from card. Includes a pull-up resistor ...
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... Refer to for additional information on the CMDVCC% and CMDVCC# operation. I Reset Input. This signal is the reset command to the card. O Signal to controller indicating the 73S8009R is ready is above the required value after CMDVCC% because V CC and/or CMDVCC# is asserted low KΩ pull-up resistor provided internally. The pull-up is disabled in DD PWRDN and CS=0 modes ...
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... Absolute Maximum Ratings Table 2 lists the maximum operating conditions for the 73S8009R. Permanent device damage may occur if absolute maximum ratings are exceeded. Exposure to the extremes of the absolute maximum rating for extended periods may affect device reliability. Table 2: Absolute Maximum Device Ratings ...
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... DS_8009R_056 2.3 Smart Card Interface Requirements Table 4 lists the 73S8009R Smart Card interface requirements. Table 4: DC Smart Card Interface Requirements Symbol Parameter Card Power Supply (V ) Regulator CC General Conditions: -40 °C < T < 85 °C, 4.75 V < Card supply voltage CC including ripple and noise ...
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... Data Sheet Symbol Parameter Interface Requirements – Data Signals: I/O, AUX1, AUX2, and host interfaces: I/OUC, AUX1UC, AUX2UC and V SHORTL SHORTH V Output level, high (I/O, OH AUX1, AUX2) V Output level, high (I/OUC, OH AUX1UC, AUX2UC) V Output level, low (I/O, OL AUX1, AUX2) V Output level, low (I/OUC, ...
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... Output rise time, fall time δ Duty cycle for CLK 2.4 Digital Signals Characteristics Table 5 lists the 73S8009R digital signals characteristics. Table 5: Digital Signals Characteristics Symbol Parameter Digital I/O except for OSC I/O V Input low voltage IL V Input high voltage ...
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... Data Sheet 2.6 Voltage / Temperature Fault Detection Circuits Table 7 lists the voltage / temperature fault detection circuits. Table 7: Voltage / Temperature Fault Detection Circuits Symbol Parameter V V fault (V Voltage PCF PC PC Supervisor threshold) V RDY = 0 CCF (V fault, V Voltage CC CC Supervisor threshold) T Die over temperature fault ...
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... This section provides general usage information for the design and implementation of the 73S8009R. 3.1 Example 73S8009R Schematics Figure 4 shows a typical application schematic for the implementation of the 73S8009R. Note that minor changes may occur to the reference material from time to time and the reader is encouraged to contact Teridian for the latest information. CS_from_uC OFF_interrupt_to_uC ...
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... Power Supply and Voltage Supervision The Teridian 73S8009R smart card interface IC incorporates a LDO voltage regulator. The voltage output is controlled by the digital input sequence on CMDVCC# and CMDVCC%. This regulator is able to provide either 1 card voltages from the power supply applied on the VPC pin. ...
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... Max Transient Min V PC Current Charge Supply required 30 nAs 4. nAs 4. VCC valid Ignored Ignored Ignored Figure 5: Activation Sequence 73S8009R Data Sheet minimum voltage and the CC PC System Requirements Power Capacitor Capacitor Type Value X5R/X7R 3.3 µF with 1 µF ESR<100 mΩ ...
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... Data Sheet Deactivation is initiated either by the system controller setting CMDVCC#/CMDVCC% high, or automatically in the event of hardware faults. Hardware faults are over-current, over-temperature and card extraction during the session. The host can manage the I/O signals, CLKIN, RSTIN, and CMDVCC#/CMDVCC% to create other de-activation sequences for non-emergency situations. ...
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... RDY - indicates VCC is OK Rev. 1.3 OFF is low by card extracted within card session OFF going high indicates circuit is ready has no effect Figure 8: Power-down Operation 73S8009R Data Sheet OFF is low by any fault within card session PWRDN will have effect when CMDVCCx=1 ~30 µs 17 ...
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... Data Sheet 3.9 Chip Select The CS pin is provided to allow multiple circuits to operate in parallel, driven from the same host control bus. When CS is high, the pins RSTIN, CMDVCC%, CMDVCC# and CLKIN control the chip as described. The pins IOUC, AUX1UC, and AUX2UC operate to transfer data to the smart card via IO, AUX1, and AUX2 when the smart card is activated. IO, AUX1, and AUX2 have 11 KΩ ...
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... Figure 11: I/O to I/OUC Delay Timing Diagram Rev. 1.3 Neutral State No I/O reception Yes I/O & not I/OUC No Yes I/OUC No & not I/O Yes I/OUC I/OICC I/OUC I/O yes yes t t I/OUC_HL I/O_LH t = 100 ns I/O_HL t = 100 ns I/OUC_HL 73S8009R Data Sheet No t I/OUC_LH I/O_LH I/OUC_LH 19 ...
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... Data Sheet 4 Mechanical Drawings 4.1 20-pin QFN 4.0 2 TOP VIEW 0.85 NOM / 0.90 MAX 0.02 NOM / 0.05 MAX 0.20 REF SEATING PLANE SIDE VIEW Figure 12: 20-pin QFN Package Dimensions 20 4.00 3. 4.0 2.0 TOP VIEW 0.18 / 0.30 2.50 / 2. BOTTOM VIEW DS_8009R_056 2 ...
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... PIN NO. 1 BEVEL .715 (18.161) .695 (17.653) .110 (2.790) .092 (2.336) Figure 13: 28-Pin SO Package Dimensions Rev. 1.3 .050 TYP. (1.270) .305 (7.747) .285 (7.239) .0115 (0.29) .003 (0.076) .016 nom (0.40) 73S8009R Data Sheet .420 (10.668) .390 (9.906) .335 (8.509) .320 (8.128) 21 ...
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... Data Sheet 5 Ordering Information Table 9 lists the order numbers and packaging marks used to identify 73S8009R products. Table 9: Order Numbers and Packaging Marks Part Description 73S8009R–SOL, 28-pin Lead-Free SO 73S8009R–SOL, 28-pin Lead-Free SO Tape / Reel 73S8009R–QFN, 20-pin Lead-Free QFN 73S8009R–QFN, 20-pin Lead-Free QFN Tape / Reel ...
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... Accordingly, the reader is cautioned to verify that a data sheet is current before placing orders. TSC assumes no liability for applications assistance. Teridian Semiconductor Corp., 6440 Oak Canyon, Suite 100, Irvine, CA 92618 TEL (714) 508-8800, FAX (714) 508-8877, http://www.teridian.com Rev. 1.3 73S8009R Data Sheet Description 23 ...