AD6620AS Analog Devices Inc, AD6620AS Datasheet
AD6620AS
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AD6620AS Summary of contents
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GENERAL DESCRIPTION The AD6620 is a digital receiver with four cascaded signal- processing elements: a frequency translator, two fixed- coefficient decimating filters, and a programmable coefficient decimating filter. All inputs are 3.3 V LVCMOS compatible. All outputs are LVCMOS ...
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AD6620 TABLE OF CONTENTS GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1 ARCHITECTURE . . . . . . . ...
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Following CIC2 is the second fixed-coefficient decimating filter. This filter, CIC5, further reduces the sample rate by a program- mable ratio from 1 to 32. The data rate out of CIC5, f determined by the decimation factors of M Each ...
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... RCF taps of alternating positive and negative full scale. CIC5 RCF = RCF taps of alternating positive and negative full scale. CIC5 RCF AD6620AS Min Typ Max 3.0 3.3 3.6 –40 +25 +85 AD6620AS Min Typ Max 3.3 V CMOS 2.0 VDD + 0.3 –0.3 0 3.3 V CMOS/TTL 2.4 VDD – 0.2 ...
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... Full V Full IV Full I Full V Full V Full V Full IV Full V Full I Full IV Full IV and t still apply. CLKH AD6620AS Min Typ Max 1 14.93 15.4 0.5 × t 7.0 CLK 0.5 × t 7.0 CLK 30.0 –1.0 6.5 8.0 19.5 7.5 19.5 6.5 19.0 5.5 11.5 7.0 19 ...
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... Full IV 3.0 Full IV 5.0 Full IV 3.0 Full IV Full IV Full IV 0.0 Full I 10.0 Full V 5.5 Full IV 0.0 Full IV 5.0 Full IV 6.5 Full IV 3.0 Full IV 0.0 Full V 5.5 AD6620AS Typ Max Unit 5 15.0 30 5 30 15.5 ...
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TIMING DIAGRAMS CLK, INPUTS, PARALLEL OUTPUTS RESET with PAR/SER = “1” establishes Parallel Outputs active. t CLK CLK t CLKL CLK IN[15:0] EXP[2:0] DATA A/B t DPR CLK DV VALID OUTPUT DATA OUT I/Q I OUT I ...
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AD6620 SERIAL PORT: BUS MASTER RESET with PAR/SER = “0” establishes Serial Port active. SBM = “1” puts AD6620 in Serial Bus Master mode SCLK is output; SDFS is output. CLK t SCLKD t SCLK SCLK t SCLKL SCLK t ...
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MICROPORT MODE0, READ Timing is synchronous to CLK; MODE = 0. 1 CLK D[7:0] t SAM A[2:0] 1 RDY NOTES: 1 RDY IS DRIVEN LOW ASYNCHRONOUSLY BY RD AND CS GOING LOW ...
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AD6620 MICROPORT MODE1, READ Timing is synchronous to CLK; MODE = 1. 1 CLK D[7:0] t SAM A[2:0] DTACK NOTES: 1 DTACK IS DRIVEN LOW ON THE RISING EDGE OF CLK ...
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... IV. Parameter Guaranteed by Design and Analysis. V. Parameter is Typical Value Only. VI. 100% Production Tested at 25°C, and Sampled Tested at Temperature Extremes. ORDERING GUIDE Package Description 80-Lead PQFP (Plastic Quad Flatpack) Evaluation Board with AD6620AS and Software AD6620 Package Option S-80A WARNING! ESD SENSITIVE DEVICE ...
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AD6620 Name Type Description VDD P 3.3 V Supply VSS G Ground CLK I Input Clock RESET I Active Low Reset Pin IN[15:0] I Input Data (Mantissa) EXP[2:0] I Input Data (Exponent) A/B I Channel (A/B) Select SYNC_NCO I/O Sync ...
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PIN CONFIGURATIONS Parallel Output Data PIN IDENTIFIER VSS VDD ...
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AD6620 –Typical Performance Characteristics 400 375 350 RCF DECIMATION 325 300 CIC5 DECIMATION 275 CIC2 DECIMATION 250 225 LOG ( –12 –24 –36 –48 –60 –72 –84 –96 –108 –120 –132 0 0 –12 –24 ...
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INPUT DATA PORT The input data port accepts a clock (CLK), a 16-bit mantissa IN[15:0], a 3-bit exponent EXP[2:0], and channel select Pin A/B. These pins allow direct interfacing to both standard fixed-point ADCs such as the AD9225 and AD6640, ...
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AD6620 The Exponent Offset is used to shift the data right. For example, Table I shows that with no ExpOff shift range is lost when the ADC input is at the largest level. This is undesired because ...
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CLK IN[15: N+1 EXP[2:0] A/B CLK 2x IF CLK 2x IS USED TO CLOCK THE AD6620, THE FIRST RISING EDGE AFTER THE A/B TRANSITION WILL LATCH THE DATA. If fractional rate ...
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AD6620 real mode with full rate timing the delay is seven CLKs. If instead the data rate is one-fourth CLK, then 28 CLKs (i.e., seven sample data delays, gated via A/B) occur before valid data is passed to the NCO ...
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WL AD SDIV SCLK SDI AD6620 SDO SDFS 10k 10k SDFE SBM +3.3V Figure 31 shows two AD6620s illustrating the cascade capability for the chip. The first is connected as a serial master and the second is configured ...
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AD6620 modes equal to f multiplied by the fraction of CLK SAMP CLK cycles on which A/B has been toggled. The NCO worst case discrete spur is better than –100 dBc for all output frequencies. The control word, ...
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REGISTER SYNC_NCO PIN REGISTER The frequency of the SYNC_NCO pulses, and therefore the accuracy of the synchronization, is determined by the value of the NCO Sync Control Register at address 302 hex. The value in this register is the ...
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AD6620 × S ceil log ( M CIC 2 2 CIC × OL input level CIC CIC 2 The equations for calculating CIC2 output level is correct when stage is ...
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SAMP 0 –20 –40 –60 –80 –100 –120 –0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 f/f SAMP2 5TH ORDER CASCADED INTEGRATOR COMB FILTER The third ...
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AD6620 CIC5 Rejection The table below illustrates the amount of bandwidth in percent- age of the clock rate that can be protected with various decimation rates and alias rejection specifications. The maximum input rate into the CIC5 is 32.5 MHz. ...
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The set of plots below (Figure 39) represents a decimation the CIC5 filter. It can be seen that the lobes of the filter drop as the decimation rate increases, but the aliased frequencies increase due to the ...
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AD6620 RCF Output Scale Factor The scale factor associated with the RCF, S ently than the scale factors in the CIC stages. This scalar, at the RCF output, controls the weight of the 16-bit output data going to the parallel ...
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Filter Phase Synchronization Like the NCO, the AD6620 filter stages have phase synchroni- zation circuitry enabling multiple AD6620s to be used in appli- cations such as diversity antennas and phased array systems. For any f , there are M possible ...
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AD6620 Address Bit Width Name 000–0FF 20 RCF Coefficient RAM 100–1FF 36 RCF Data RAM 200–27F 0 Reserved 300 8 MODE CONTROL REGISTER 301 3 NCO CONTROL REGISTER 302 32 NCO SYNC CONTROL REGISTER 303 32 NCO_FREQ 304 16 NCO ...
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The NCO has two features to improve the performance of some systems: Phase Dither and Amplitude Dither. These can be used together or alone. If Bit 1 of the register is high, Phase Dither is activated. If Bit 2 is ...
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AD6620 PROGRAMMING THE AD6620 Initializing the AD6620 Before the AD6620 can be used to down convert and filter the channel of interest it must be configured for the job. First the RESET pin should be pulsed low for a minimum ...
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ACCESS PROTOCOLS The AD6620 external accesses may be performed through either the Microprocessor Port or the Serial Port. The Microport and the serial port both use a three-bit address and eight-bit data to access these registers. The three-bit address provides ...
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AD6620 Read Pseudocode int read_micro(ext_address); main(); { / This code shows the reading of the NCO frequency register using the read_micro function as defined above. The variable address is the External Address A[2..0] and data is the value to be ...
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Mode = 0 If MODE is low during the access, the interface is in Mode 0. In Mode 0 the CS, RD and the WR lines control the access type. While an access is being performed the serial ...
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AD6620 Mode = 1 If the MODE input is held high the interface is in Mode 1. In Mode 1 the RD signal becomes the data strobe (DS) and the WR signal becomes a read/write (R/W) select signal. In this ...
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SERIAL PORT CONTROL In addition to providing access to the complex output data stream of the AD6620, the Serial Port can also be used for Dynamic Control of the device. The dynamic registers of the AD6620 that are typically programmed ...
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AD6620 Example of Serial Port W/R Operation The example shown below demonstrates writing and reading from the AD6620. For this example, the chip is set up in diver- sity channel real mode. Therefore, there four data words (two Is and ...
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Master AD6620, the SDFE signal will be driven high by the same SCLK rising edge that this bit is clocked out on. On the falling edge of this SCLK cycle, the Cascaded AD6620 will sample its SDFS signal, which is ...
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AD6620 APPLICATIONS EVALUATION BOARD An evaluation board is available for the AD6620. This evalua- tion board comes complete with an AD6620 and interfaces through the printer port. The evaluation board comes com- plete with software to drive ...
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SDO of the master AD6620 takes control of the SDO line and begins shifting data out of the device. When all data has been shifted, the master raises the SDFE on the last shifted. This signals the next chip ...
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AD6620 bit set mode1 SRD1H | SRD2L | SRRFH | SRRFL; nop; / Insert code here to process I and Q data. The DSP serial port handler has placed the samples in fm_demod_data and fm_demod_data+1 / pop sts; / Pop ...
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The impulse response length of the CIC2 is given by ( × − CIC 2 f ADC The composite impulse response length of all three stages is × × + × TAPS CIC ...
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AD6620 PARALLEL PROCESSING USING AD6620 If a single AD6620 does not have enough time to compute an adequate filter, multiple AD6620s can be operated in parallel as shown in Figure 56. In this example, the processing is distrib- uted between ...
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INPUT LATCHING D OUT1 CLOCK DV OUT1 INPUT LATCHING D OUT2 CLOCK DV OUT2 D INPUT LATCHING OE OUT3 CLOCK DV OUT3 D INPUT LATCHING OE OUT4 CLOCK DV OUT4 In the Output Selector above each of the DV with ...
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AD6620 A DSP is then used to perform the demodulation of the digital channel. This has the advantage of allowing for in-system con- figuration options and can even allow for improved modulation techniques to be applied in the future. This ...