S1D13743F00A200 Epson, S1D13743F00A200 Datasheet
S1D13743F00A200
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S1D13743F00A200 Summary of contents
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... You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners ...
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... Page 2 S1D13743 X70A-A-001-02 Epson Research and Development Revision 2.7 Vancouver Design Center Hardware Functional Specification Issue Date: 2010/05/18 ...
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... Epson Research and Development Vancouver Design Center 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2 Overview Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 Integrated Frame Buffer 2.2 CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 Input Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 Display Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5 Display Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.6 Display Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.7 Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.8 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 Pins ...
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... Mode 2 (R 6-bit, G 6-bit, B 6-bit), 262,144 colors . . . . . . . . . . . . . .80 14.4 24 bpp Mode 1 (R 8-bit, G 8-bit, B 8-bit), 16,777,216 colors 14.5 24 bpp Mode 2 (R 8-bit, G 8-bit, B 8-bit), 16,777,216 colors S1D13743 X70A-A-001 .75 Revision 2.7 Epson Research and Development Vancouver Design Center . . . . . . . . . . . . .82 Hardware Functional Specification Issue Date: 2010/05/18 ...
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... Epson Research and Development Vancouver Design Center 15 YUV Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 15.1 YUV 4:2:2 with Intel 80, 8-bit Interface . . . . . . . . . . . . . . . . . . . . 84 15.2 YUV 4:2:0 ODD Line with Intel 80, 8-bit Interface . . . . . . . . . . . . . . . . 84 15.3 YUV 4:2:0 EVEN Line with Intel 80, 8-bit Interface . . . . . . . . . . . . . . . 85 15.4 YUV 4:2:2 with Intel 80, 16-bit Interface . . . . . . . . . . . . . . . . . . . . 86 15 ...
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... PLL Power Supply Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . 120 22.1 Guidelines for PLL Power Layout . . . . . . . . . . . . . . . . . . . . . . 120 23 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 24 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 25 Sales and Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 25.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 S1D13743 X70A-A-001-02 Epson Research and Development Revision 2.7 Vancouver Design Center Hardware Functional Specification Issue Date: 2010/05/18 ...
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... This document is intended for two audiences: Video Subsystem Designers and Software Developers. This document is updated as appropriate. Please check the Epson Research and Devel- opment Website at www.erd.epson.com for the latest revision of this document before beginning any development. ...
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... Note All data is stored as 24 bpp. 18-bit panels are supported using the 18 msb’s when FRM is disabled or all 24 bits when FRM is enabled. S1D13743 X70A-A-001-02 Epson Research and Development Revision 2.7 Vancouver Design Center Hardware Functional Specification Issue Date: 2010/05/18 ...
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... Epson Research and Development Vancouver Design Center 2.6 Display Features • All display writes are handled by window apertures/position for complete or partial display updates. All window coordinates are referenced from the top left corner of the displayed image. Even for a rotated display, the top-left corner is maintained and no translation needs to take place. • ...
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... MClk Rotation LCD Disp Memory Pipe Controller (Pixel Halving) MClk Double Buffer Controller Figure 3-1: Block Diagram Revision 2.7 Epson Research and Development Vancouver Design Center Data Control PClk PClk PClk LCD Gamma FRM IF Correction PClk LCD Ctc Hardware Functional Specification ...
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... Epson Research and Development Vancouver Design Center 4 Pins 4.1 Pinout Diagrams CLKOUT B NC MD2 MD12 C MD0 MD11 MD1 D RESET# TE GPIO_INT E TEST1 TEST2 TESTEN F TEST0 SCANEN CNF0 G GPIO0 GPIO1 CNF1 H GPIO2 GPIO3 CNF2 J GPIO4 GPIO5 PWRSVE K NC GPIO6 GPIO7 VD6 Figure 4-1: S1D13743 FCBGA Pinout (Top View) ...
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... IOVDD 140 VSS MD9 141 142 RD# MD10 143 144 D/C# 144 Figure 4-2: S1D13743 QFP20 Pinout (Top View) S1D13743 X70A-A-001- INDEX Revision 2.7 Epson Research and Development Vancouver Design Center 73 72 GPIO4 72 GPIO5 71 PWRSVE 70 VSS 69 IOVDD 68 GPIO6 67 GPIO7 66 VSS 65 COREVDD ...
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... Epson Research and Development Vancouver Design Center 4.2 Pin Descriptions Key: Pin Types I = Input O = Output IO = Bi-Directional (Input/Output Power pin RESET# / Power Save Status H = High level output L = Low level output Hi-Z = High Impedance Item System LVCMOS HIS H System LVCMOS Schmitt Input Buffer ...
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... IOVDD L HIS IOVDD Input Input Revision 2.7 Epson Research and Development Vancouver Design Center Description Intel 80 Host Data lines 15-0. Note: The Host Data Lines can be swapped (i.e. D15 = D0) using the CNF0 pin. For details, see Section 4.3, “Summary of Configuration Options” on page 18. ...
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... Epson Research and Development Vancouver Design Center 4.2.2 LCD Interface FCBGA QFP Pin Name Type Pin # Pin # H10, H11, 12,13,60, J4, J5, J6, 55,50,45, J7, J8, J9, 40,20,14, J10, J11, 15,61,56, VD[23:0] IO K4, K5, K6, 51,48,44, K7, K8, K9, 38,21,63, K10, L3, L4, 62,57,54, L5, L6, L7, 49,43,39 L8 D10 PCLK O D11 ...
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... LITR PLLVDD — — — — Revision 2.7 Epson Research and Development Vancouver Design Center Description These inputs are used for power-up configuration. For further details, see Section 4.3, “Summary of Configuration Options” on page 18. Note: These pins must be connected directly to IOVDD or VSS. ...
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... Epson Research and Development Vancouver Design Center 4.2.5 Power And Ground Table 4-5: Power And Ground Pin Descriptions Pin Name Type FCBGA Pin # 6,26,41,52,64,74, COREVDD P D7, E4, G7, H6 IOVDD P C4, D8, H4 PIOVDD P E8, G4, H5, H7 PLLVDD P D4 PLLVSS P D6 C5, C6, E5, E6, VSS P E7, F4, F5, F6, ...
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... X70A-A-001-02 Power-On/Reset State ) 0 (Connected Host Data Lines are swapped: If CNF1 = 1b, then D15 = D0, etc. If CNF1 = 0b, then D7 = D0, etc. Host Data is 8-bit (see Note) PIOVDD output current = 2.5mA Revision 2.7 Epson Research and Development Vancouver Design Center Hardware Functional Specification Issue Date: 2010/05/18 ...
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... Epson Research and Development Vancouver Design Center 5 Pin Mapping 5.1 Intel 80 Data Pins Intel 80 data pin mapping is controlled by CNF[1:0]. For details on CNF[1:0], see Section 4.3, “Summary of Configuration Options” on page 18. 16-Bit Data Pin Name No Swap (CNF1=1b, CNF0=1b) MD15 MD15 • • ...
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... No Swap REG[14h] bit • • Driven Low • VD17 • • • • • • VD0 Revision 2.7 Epson Research and Development Vancouver Design Center 24-Bit Data Swapped REG[14h] bit VD0 • • • VD5 VD6 • • • VD23 18-Bit Data ...
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... Epson Research and Development Vancouver Design Center 6 D.C. Characteristics 6.1 Absolute Maximum Ratings Symbol Parameter Core V Core Supply Voltage DD PLL V PLL Supply Voltage Host IO Supply Voltage DD PIO V Panel IO Supply Voltage DD V Input Signal Voltage IN V Output Signal Voltage OUT I Output Signal Current OUT 6 ...
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... CMOS Schmitt V = VSS VDD VSS VDD 1MHz, VDD = 0V = 1.5V CORE = 1.8V HIO = 1.8V PIO Revision 2.7 Epson Research and Development Vancouver Design Center , Min Typ Max — 100 — — 500 1000 — — 74 — 9.2 — — 667 — — ...
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... Epson Research and Development Vancouver Design Center The following characteristics are for: IOVDD, VSS = 0V, T Table 6-4: Electrical Characteristics for IOVDD or PIOVDD = 3.3V ± 0.3V Symbol Parameter I Quiescent Current QALL I PLL Current PLL I Operation Peak Current CORE I Input Leakage Current IZ I Output Leakage Current ...
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... Page 24 7 A.C. Characteristics 7.1 Clock Timing 7.1.1 Input Clocks 90 CLKI CLKI S1D13743 X70A-A-001- OSC t t OSC Figure 7-1 Clock Input Required (CLKI) Revision 2.7 Epson Research and Development Vancouver Design Center t2 OSC Hardware Functional Specification Issue Date: 2010/05/18 ...
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... Epson Research and Development Vancouver Design Center Symbol Input clock frequency - PLL used for System Clock f OSC (see note 1) Input clock frequency - CLKI used for System Clock t Input clock period OSC t1 Input clock pulse width high t2 Input clock pulse width low ...
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... X70A-A-001-02 PLL Stable 10 ms Lock In Time PLL xxMHz Output (xx = 44.28~66.53MHz) Lock in time 10 ms Time (ms) Figure 7-2: PLL Start-Up Time Table 7-2: PLL Clock Requirements Parameter Revision 2.7 Epson Research and Development Vancouver Design Center Min Max Units 44.28 (Note 1) 66.53 MHz - ...
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... Epson Research and Development Vancouver Design Center 7.2 RESET# Timing RESET# CLKI Symbol t1 Active Reset Pulse Width Hardware Functional Specification Issue Date: 2010/05/ CLKI Figure 7-3 S1D13743 RESET# Timing Table 7-3 S1D13743 RESET# Timing Parameter Revision 2.7 Page 27 Min Max Units 1 — ...
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... When CNF1=1, MD[15:0] are used for accesses to the Memory Data Port. MD[7:0] are used for all other accesses. Figure 7-4: Intel 80 Input A.C. Characteristics - 1.8 Volt S1D13743 X70A-A-001-02 t wcs dst t rcs rdd t rdv Revision 2.7 Epson Research and Development Vancouver Design Center t wah t csf ch t csf r2w t w2r t dht t rah ...
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... Epson Research and Development Vancouver Design Center Table 7-4: Intel 80 Input A.C. Characteristics - 1.8 Volt Signal Symbol Parameter t Address setup time (read/write) ast D/C# t Address hold time (write) wah t Address hold time (read) rah t Chip Select setup time (write) wcs t Chip Select setup time (read) ...
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... When CNF1=1, MD[15:0] are used for accesses to the Memory Data Port. MD[7:0] are used for all other accesses. Figure 7-5: Intel 80 Input A.C. Characteristics - 3.3 Volt S1D13743 X70A-A-001-02 t wcs dst t rcs rdd t rdv Revision 2.7 Epson Research and Development Vancouver Design Center t wah t csf ch t csf r2w t w2r t dht t rah ...
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... Epson Research and Development Vancouver Design Center Table 7-5: Intel 80 Input A.C. Characteristics - 3.3 Volt Signal Symbol Parameter t Address setup time (read/write) ast D/C# t Address hold time (write) wah t Address hold time (read) rah t Chip Select setup time (write) wcs t Chip Select setup time (read) ...
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... Nch- pLZ Internal logic delay + t (from High to Hi-Z) pHZ to measure t IOVDD VSS to measure t Volt P IOVDD IOVDD ½ 0.2 IOVDD Time Revision 2.7 Epson Research and Development Vancouver Design Center pHZ pLZ EN N Time t pLZ Hardware Functional Specification Issue Date: 2010/05/18 ...
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... Epson Research and Development Vancouver Design Center 7.4 Display Interface The timing parameters required to drive a flat panel display are shown below. Timing details for each supported panel type are provided in the remainder of this section VPS VSW Table 7-6: Panel Timing Parameter Definition and Register Summary ...
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... Table 7-7: TFT Power-On Sequence Timing Symbol t1 Power Save Mode disabled to LCD signals active S1D13743 X70A-A-001-02 t1 Figure 7-8: TFT Power-On Sequence Timing Parameter Revision 2.7 Epson Research and Development Vancouver Design Center Min Max Units Hardware Functional Specification Issue Date: 2010/05/18 ...
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... Epson Research and Development Vancouver Design Center 7.4.2 TFT Power-Off Sequence Power Save Mode Enable* (REG[56h] bits 1-0) LCD Signals** *The LCD power-off sequence is activated by programming the Power Save Register (REG[56h]) bit 1 or bit enabling the PWRSVE pin (see REG[56h] bit 7). ...
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... Note HS, VS, PCLK all have Polarity Select bits via registers S1D13743 X70A-A-001- t18 t5 t6 t12 t12 invalid Figure 7-10: 18/24-Bit TFT A.C. Timing Revision 2.7 Epson Research and Development Vancouver Design Center t13 t14 t14 t13 t15 t16 1 2 320 invalid ...
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... Epson Research and Development Vancouver Design Center Symbol VS cycle time t1 VS pulse width low t2 VS falling edge to HS falling edge phase difference t3 HS cycle time t4 HS pulse width low t5 HS Falling edge to DE active t6 DE pulse width falling edge to HS falling edge ...
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... Revision 2.7 Epson Research and Development Vancouver Design Center Hardware Functional Specification Issue Date: 2010/05/18 ...
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... Epson Research and Development Vancouver Design Center Table 8-2: Memory Map for Double Buffer (REG[36h] bit 6 = 1b) Hardware Functional Specification Issue Date: 2010/05/18 Memory Description Address 00000h green [7:0] for pixel 1, buffer 1 00001h red [7:0] for pixel 1, buffer 1 00002h green [7:0] for pixel 2, buffer 1 ...
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... CLKOUT S1D13743 X70A-A-001-02 Clock Source Select (REG[12h] bit 0) Glitch Free 1 0 PCLK Divide Select (REG[12h] bits 7-3) Figure 9-1: S1D13743 Clock Block Diagram Revision 2.7 Epson Research and Development Vancouver Design Center SYSCLK Divider 1 2 PCLK 3 • • • 32 Hardware Functional Specification ...
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... Epson Research and Development Vancouver Design Center 9.2 PLL Block Diagram REG[04h] bits 5-0 PLLCLK CLKI M-Divider REG[0Eh] bits 6-0 L-Counter Where: PFD = Phase Frequency Detector CP = Charge Pump VCO = Voltage Controlled Oscillator Loop Filter = Low Pass Filter TEST Control = Internal Control Logic ...
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... Register accesses do not require an internal clock as the S1D13743 creates a clock from the bus cycle alone. S1D13743 X70A-A-001-02 Table 9-1: Internal Clock Requirements Internal SYSCLK No Yes Yes No Yes Revision 2.7 Epson Research and Development Vancouver Design Center Internal PCLK Yes Hardware Functional Specification Issue Date: 2010/05/18 ...
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... Epson Research and Development Vancouver Design Center 9.4 Setting SYSCLK and PCLK The period of the system clock, TSYSCLK, must be set such that it falls within the following range: For PLL: For CLKI: where T BBC For example, if the minimum back-to-back cycle time of the Intel 80 Interface is 47.5ns, ...
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... Memory Data Port (REG[48h ~ 49h]) which is accessed according to the configuration of the CNF1 pin (16-bit for CNF1 = 1b, 8-bit for CFN1 = 0b). For further information on this setting, see Section 4.3, “Summary of Configuration Options” on page 18. S1D13743 X70A-A-001-02 Epson Research and Development Revision 2.7 Vancouver Design Center Hardware Functional Specification Issue Date: 2010/05/18 ...
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... Epson Research and Development Vancouver Design Center 10.2 Register Set The S1D13743 registers are listed in the following table. Register REG[00h] Revision Code Register REG[04h] PLL M-Divider Register REG[08h] PLL Setting Register 1 REG[0Ch] PLL Setting Register 3 REG[10h] REG[14h] Panel Type Register REG[18h] Horizontal Non-Display Period Register (HNDP) ...
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... These read-only status bits return the status of the configuration pins CNF[2:0]. For details on CNF[2:0] functionality, see Section 4.3, “Summary of Configuration Options” on page 18. S1D13743 X70A-A-001-02 Product Code bits 5 n Revision 2.7 Epson Research and Development Vancouver Design Center Read Only Revision Code bits 1 Read Only CNF2 Status CNF1 Status CNF0 Status ...
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... Epson Research and Development Vancouver Design Center 10.3.2 Clock Configuration Registers REG[04h] PLL M-Divider Register Default = 00h PLL Lock (RO) n bit 7 PLL Lock (Read Only) This bit indicates the status of the PLL output. When this bit = 0, the PLL output is not stable. In this state read/write access to the display buffer is prohibited ...
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... This register must be programmed with the value 28h. S1D13743 X70A-A-001-02 PLL Setting Register 0 bits 7 PLL Setting Register 1 bits 7 PLL Setting Register 2 bits 7 Revision 2.7 Epson Research and Development Vancouver Design Center Read/Write Read/Write Read/Write Hardware Functional Specification Issue Date: 2010/05/18 ...
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... Epson Research and Development Vancouver Design Center REG[0Ch] PLL Setting Register 3 Default = 00h 7 6 This register must be programmed with the value 00h. REG[0Eh] PLL Setting Register 4 Default = 00h n bits 6-0 L-Counter bits [6:0] These bits are used to configure the PLL Output (in MHz) and must be set according to the following formula ...
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... Revision 2.7 Epson Research and Development Vancouver Design Center Read/Write SYSCLK Source n/a Select PCLK Divide Ratio 17:1 18:1 19:1 20:1 21:1 22:1 23:1 24:1 ...
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... Epson Research and Development Vancouver Design Center bit 0 SYSCLK Source Select This bit selects the source of the system clock (SYSCLK) for the S1D13743. When this bit = 0, the SYSCLK source is the external CLKI input. When this bit = 1, the SYSCLK source is the internal PLL. ...
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... The minimum Horizontal Non-Display Period is 3 Pixels (REG[18h] bits 6-0 = 03h). HS Start + HS Width <= HNDP S1D13743 X70A-A-001-02 n Horizontal Display Width bits 6 Horizontal Non-Display Period bits 6 Revision 2.7 Epson Research and Development Vancouver Design Center Read/Write Panel Data Width Read/Write Read/Write Hardware Functional Specification Issue Date: 2010/05/18 ...
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... Epson Research and Development Vancouver Design Center REG[1Ah] Vertical Display Height Register 0 (VDISP) Default = 01h 7 6 REG[1Ch] Vertical Display Height Register 1 (VDISP) Default = 00h 7 6 REG[1Ch] bits 1-0 REG[1Ah] bits 7-0 Vertical Display Height bits [9:0] These bits specify the Vertical Display Height (VDISP) for the LCD panel, in lines. ...
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... When this bit = 1, data is output on the falling edge of PCLK. S1D13743 X70A-A-001-02 HS Pulse Start Position bits 6 Pulse Width bits 5 Pulse Start Position bits 7 n Revision 2.7 Epson Research and Development Vancouver Design Center Read/Write Read/Write Read/Write Read/Write Hardware Functional Specification Issue Date: 2010/05/18 ...
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... Epson Research and Development Vancouver Design Center 10.3.4 Input Mode Register REG[2Ah] Input Mode Register Default = 01h n bits 3-0 Input Data Format bits [3:0] These bits select the input data format. For further information on Input Data Format and Memory Data Format, see Section 13, “Intel 80, 8-bit Interface Color Formats” on page 75, Section 14, “ ...
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... Table 10-6: UV Fix Selection UV Input to the YRC Original U data, original V data U data = REG[32h] bits 7-0, original V data Original U data, V data = REG[34h] bits 7-0 U data = REG[32h] bits 7-0, V data = REG[34h] bits 7-0 Revision 2.7 Epson Research and Development Vancouver Design Center Read/Write n ...
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... Epson Research and Development Vancouver Design Center REG[2Eh] Input YUV/RGB Translate Mode Register 1 Default = 05h Reserved YUV Input Data Type Select bits 1 bits 7-6 Reserved The default value for these bits is 00b. bits 5-4 YUV Input Data Type Select bits [1:0] These bits specify the data type of the YUV input to the YUV to RGB Converter (YRC) ...
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... Recommended for ITU-R BT.470-6 System M Recommended for ITU-R BT.470-6 System B, G (Recommended for ITU-R BT.601-5) SMPTE 170M SMPTE 240M(1987) U Data Fix bits 7 Data Fix bits 7 Revision 2.7 Epson Research and Development Vancouver Design Center Read/Write Read/Write Hardware Functional Specification Issue Date: 2010/05/18 ...
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... Epson Research and Development Vancouver Design Center 10.3.5 Display Mode Registers REG[34h] Display Mode Register Default = 08h Display Blank FRM Mode Select bits 2 bit 7 Display Blank This bit blanks the display by disabling the LCD display pipeline and forcing all LCD data outputs to zero ...
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... Single buffered window with no double buffering anywhere on the display. Use this to write a single buffered window while preventing tearing in a previously defined double buffered window. Reserved Use this to write data to be double buffered. Revision 2.7 Epson Research and Development Vancouver Design Center 0° (Normal) 90° 180° 270° ...
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... Epson Research and Development Vancouver Design Center bit 6 Double Buffer Enable This bit is used in conjunction with the Window Data Type bit (REG[36h] bit 7) and con- trols the Double Buffer architecture. Double buffering is intended to prevent visual tearing when updating the display from streaming input sources. This bit must be set before the window data is written, as the window coordinates will be latched internally to be used by the display pipe during display cycles ...
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... Table 10-12: Window Pixel Sizing REG[36h] bits 1-0 Result 00b No Resizing 01b Pixel Doubling 10b Pixel Halving 11b Reserved Display Original Window Pixel Doubled Window Figure 10-1: Sizing Example Revision 2.7 Epson Research and Development Vancouver Design Center Hardware Functional Specification Issue Date: 2010/05/18 ...
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... Epson Research and Development Vancouver Design Center 10.3.6 Window Settings REG[38h] Window X Start Position Register 0 Default = 00h 7 6 REG[3Ah] Window X Start Position Register 1 Default = 00h 7 6 REG[3Ah] bits 1-0 REG[38h] bits 7-0 Window X Start Position bits [9:0] These bits determine the X start position of the window in relation to the top left corner of the displayed image ...
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... S1D13743 X70A-A-001-02 Window X End Position bits 7 n Window Y End Position bits 7 n Revision 2.7 Epson Research and Development Vancouver Design Center Read/Write Read/Write Window X End Position bits 9 Read/Write Read/Write Window Y End Position bits 9 Hardware Functional Specification ...
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... Epson Research and Development Vancouver Design Center 10.3.7 Memory Access REG[48h] Memory Data Port Register 0 Default = not applicable 7 6 REG[49h] Memory Data Port Register 1 Default = not applicable 7 6 REG[48h] bits 7-0 Memory Data Port bits [7:0] These bits specify the lsb of the data word. ...
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... Read Address bit 0 is ignored and internally forced to 0b. S1D13743 X70A-A-001-02 Memory Read Address bits 7 Memory Read Address bits 15 n Revision 2.7 Epson Research and Development Vancouver Design Center Read/Write Read/Write Read/Write Memory Read Address bit 18- Hardware Functional Specification Issue Date: 2010/05/18 ...
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... Epson Research and Development Vancouver Design Center 10.3.8 Gamma Correction Registers Note Gamma correction is implemented as a look-up table. RGB input data (YUV input data is converted to RGB) is used to look-up the values from the programmed tables. The Gamma LUT’s are placed on the display read path and the 24-bit output goes to the LCD interface ...
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... Note When performing auto-increment writes, all 256 positions of each LUT must be written. S1D13743 X70A-A-001-02 Gamma Correction Table Index bits 7 Gamma Correction Table Data bits 7 Revision 2.7 Epson Research and Development Vancouver Design Center Read/Write Read/Write Hardware Functional Specification Issue Date: 2010/05/18 ...
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... Epson Research and Development Vancouver Design Center 10.3.9 Miscellaneous Registers REG[56h] Power Save Register Default = 00h PWRSVE Input Pin Function 7 6 bit 7 PWRSVE Input Pin Function This bit determines the functionality of the PWRSVE input pin. When this bit = 0, the PWRSVE pin is OR’d with the Sleep Mode Enable/Disable bit (REG[56h] bit 1) and setting either to 1 will enable Sleep Mode. When this bit = 1, the PWRSVE pin is OR’ ...
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... Table 10-14: TE Output Pin Function Selection REG[58h] bits 1-0 S1D13743 X70A-A-001-02 TE Output Pin Function 00b Reserved 01b Horizontal Non-Display Period 10b Vertical Non-Display Period 11b HS OR’d with VS Revision 2.7 Epson Research and Development Vancouver Design Center Hardware Functional Specification Issue Date: 2010/05/18 ...
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... Epson Research and Development Vancouver Design Center 10.3.10 General Purpose IO Pins Registers REG[5Ah] General Purpose IO Pins Configuration Register 0 Default =00h GPIO7 GPIO6 GPIO5 Configuration Configuration Configuration 7 6 bits 7-0 GPIO[7:0] Configuration These bits configure the corresponding GPIO[7:0] pin between inputs or outputs. ...
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... GPIO4 Interrupt GPIO3 Interrupt Status Status GPIO4 Pull-down GPIO3 Pull-down Control Control Revision 2.7 Epson Research and Development Vancouver Design Center Read/Write GPIO2 Negative GPIO1 Negative GPIO0 Negative Edge Interrupt Edge Interrupt Edge Interrupt Trigger Trigger Trigger Read/Write GPIO2 Interrupt ...
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... Epson Research and Development Vancouver Design Center 11 Frame Rate Calculation The following formula is used to calculate the display frame rate. Where: f PCLK HT VT Note For definitions of panel timing parameters, see Section 7.4, “Display Interface” on page 33. Hardware Functional Specification Issue Date: 2010/05/18 ...
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... Bit 7 Bit 6 Bit 5 Bit Bit 7 Bit 6 Bit 5 Bit Table 12-3: RGB 8:8:8 Memory Format Bit 7 Bit 6 Bit 5 Bit Revision 2.7 Epson Research and Development Vancouver Design Center Bit 3 Bit 2 Bit 1 Bit Bit 3 Bit 2 Bit 1 Bit Bit 3 Bit 2 Bit 1 Bit Hardware Functional Specification ...
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... Epson Research and Development Vancouver Design Center 13 Intel 80, 8-bit Interface Color Formats 13.1 16 bpp Mode (R 5-bit, G 6-bit, B 5-bit), 65,536 colors CS# D/C# WR# RD# MD7 Bit 7 MD6 Bit 6 MD5 Bit 5 MD4 Bit 4 MD3 Bit 3 MD2 Bit 2 MD1 Bit 1 MD0 Bit 0 Note: The Data order is as follows, MSB = MD7, LSB = MD0 and Picture Data is MSB = Bit 5, LSB = Bit 0 for Green data and MSB = Bit 4, LSB = Bit 0 for Red and Blue data ...
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... G1, Bit 2 Bit 3 R1, Bit 1 G1, Bit 1 Bit 2 R1, Bit 0 G1, Bit 0 Bit 1 Bit 0 Pixel n Revision 2.7 Epson Research and Development Vancouver Design Center B1, Bit 5 R2, Bit 5 B1, Bit 4 R2, Bit 4 B1, Bit 3 R2, Bit 3 B1, Bit 2 R2, Bit 2 B1, Bit 1 R2, Bit 1 ...
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... Epson Research and Development Vancouver Design Center 13.3 24 bpp (R 8-bit, G 8-bit, B 8-bit), 16,777,216 colors CS# D/C# WR# RD# MD7 Bit 7 MD6 Bit 6 MD5 Bit 5 MD4 Bit 4 MD3 Bit 3 MD2 Bit 2 MD1 Bit 1 MD0 Bit 0 Note: The Data order is as follows, MSB = MD7, LSB = MD0 and Picture Data is MSB = Bit 7, LSB = Bit 0. ...
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... B1, Bit 2 B2, Bit 2 B1, Bit 1 B2, Bit 1 Bit 1 B1, Bit 0 B2, Bit 0 Bit 0 Pixel n Pixel Revision 2.7 Epson Research and Development Vancouver Design Center R3, Bit 4 R3, Bit 3 R3, Bit 2 R3, Bit 1 R3, Bit 0 G3, Bit 5 G3, Bit 4 G3, Bit 3 G3, Bit 2 ...
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... Epson Research and Development Vancouver Design Center 14.2 18 bpp Mode 1 (R 6-bit, G 6-bit, B 6-bit), 262,144 colors CS# D/C# WR# RD# MD15 MD14 MD13 MD12 MD11 MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 Note: The Data order is as follows, MSB = MD15, LSB = MD0 and Picture Data is MSB = Bit 5, LSB = Bit 0. ...
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... B2, Bit 2 Bit 3 R1, Bit 1 B2, Bit 1 R1, Bit 0 Bit 2 B2, Bit 0 Bit 1 Bit 0 Pixel n Revision 2.7 Epson Research and Development Vancouver Design Center R2, Bit 5 R2, Bit 4 R2, Bit 3 R2, Bit 2 R2, Bit 1 R2, Bit 0 Pixel Hardware Functional Specification Issue Date: 2010/05/18 ...
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... Epson Research and Development Vancouver Design Center 14.4 24 bpp Mode 1 (R 8-bit, G 8-bit, B 8-bit), 16,777,216 colors CS# D/C# WR# RD# MD15 MD14 MD13 MD12 MD11 MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 Note: The Data order is as follows, MSB = MD15, LSB = MD0 and Picture Data is MSB = Bit 7, LSB = Bit 0. ...
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... Bit 2 R1, Bit 2 B1, Bit 2 Bit 1 R1, Bit 1 B1, Bit 1 R1, Bit 0 Bit 0 B1, Bit 0 Pixel n Revision 2.7 Epson Research and Development Vancouver Design Center R2, Bit 7 R2, Bit 6 R2, Bit 5 R2, Bit 4 R2, Bit 3 R2, Bit 2 R2, Bit 1 R2, Bit 0 Pixel ...
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... Epson Research and Development Vancouver Design Center 15 YUV Timing Format Definition • The number of pixels per line is always even • The YC • YUV 4:2:2 format • YUV 4:2:0 format Note When a window is setup for YUV data, the data must always alternate between odd and even lines, starting with an odd line ...
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... Figure 15-2: YUV 4:2:2 with Intel 80, 8-bit Interface 15.2 YUV 4:2:0 ODD Line with Intel 80, 8-bit Interface Figure 15-3: YUV 4:2:0 ODD Line with Intel 80, 8-bit Interface S1D13743 X70A-A-001-02 Epson Research and Development Revision 2.7 Vancouver Design Center Hardware Functional Specification Issue Date: 2010/05/18 ...
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... Epson Research and Development Vancouver Design Center 15.3 YUV 4:2:0 EVEN Line with Intel 80, 8-bit Interface Figure 15-4: YUV 4:2:0 EVEN Line with Intel 80, 8-bit Interface Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 Page 85 S1D13743 X70A-A-001-02 ...
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... Page 86 15.4 YUV 4:2:2 with Intel 80, 16-bit Interface Figure 15-5: YUV 4:2:2 with Intel 80, 16-bit Interface S1D13743 X70A-A-001-02 Epson Research and Development Revision 2.7 Vancouver Design Center Hardware Functional Specification Issue Date: 2010/05/18 ...
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... Epson Research and Development Vancouver Design Center 15.5 YUV 4:2:0 ODD Line with Intel 80, 16-bit Interface Figure 15-6: YUV 4:2:0 ODD Line with Intel 80, 16-bit Interface Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 Page 87 S1D13743 X70A-A-001-02 ...
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... Page 88 15.6 YUV 4:2:0 EVEN Line with Intel 80, 16-bit Interface Figure 15-7: YUV 4:2:0 EVEN Line with Intel 80, 16-bit Interface S1D13743 X70A-A-001-02 Epson Research and Development Revision 2.7 Vancouver Design Center Hardware Functional Specification Issue Date: 2010/05/18 ...
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... Epson Research and Development Vancouver Design Center 16 Gamma Correction Look-Up Table Architecture The following figure is intended to show the display data output path only. The following diagram shows the architecture for 24 bpp using the LUT. Red Look-Up Table 256x8 00h 01h 02h ...
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... Write data to the Gamma Correction Table Data register (data value for Index “x+1”) • Continue until all 256 positions have been written • Enable Gamma Correction (REG[50h] bit S1D13743 X70A-A-001-02 Epson Research and Development Revision 2.7 Vancouver Design Center Hardware Functional Specification Issue Date: 2010/05/18 ...
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... Epson Research and Development Vancouver Design Center 17 Display Data Format Table 17-1: 24-Bit Data Format (Non-Swapped, REG[14h] bit 7 = 0b) Pin Name 1 VD23 R 0 VD22 R 0 VD21 R 0 VD20 R 0 VD19 R 0 VD18 R 0 VD17 R 0 VD16 R 0 VD15 G 0 VD14 G 0 VD13 ...
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... VD17 B 0 VD16 B 0 VD15 G VD14 G VD13 G VD12 G VD11 G VD10 G VD9 G VD8 G VD7 R VD6 R VD5 R VD4 R VD3 R VD2 R VD1 R VD0 R S1D13743 X70A-A-001-02 Cycle Count Revision 2.7 Epson Research and Development Vancouver Design Center ... n 0 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... R n Hardware Functional Specification Issue Date: 2010/05/18 ...
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... Epson Research and Development Vancouver Design Center Table 17-3: 18-Bit Data Format (Non-Swapped, REG[14h] bit 7 = 0b) Pin Name 1 VD[23:18] VD17 R 0 VD16 R 0 VD15 R 0 VD14 R 0 VD13 R 0 VD12 R 0 VD11 G 0 VD10 G 0 VD9 G 0 VD8 G 0 VD7 G 0 VD6 ...
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... VD14 B 0 VD13 B 0 VD12 B 0 VD11 G VD10 G VD9 G VD8 G VD7 G VD6 G VD5 R VD4 R VD3 R VD2 R VD1 R VD0 R S1D13743 X70A-A-001-02 Cycle Count 2 3 Low Revision 2.7 Epson Research and Development Vancouver Design Center ... n 2 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... R n Hardware Functional Specification Issue Date: 2010/05/18 ...
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... Epson Research and Development Vancouver Design Center 18 SwivelView™ 18.1 Concept Most computer displays are refreshed in landscape orientation – from left to right and top to bottom. Computer images are stored in the same manner. SwivelView™ is designed to rotate the displayed image on a LCD by 90°, 180°, or 270° counter-clockwise direction. ...
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... REG[34h] bits 1-0). All Start Addresses and Line Offsets are automatically calculated by hardware. S1D13743 X70A-A-001-02 B display start address (panel origin) Revision 2.7 Epson Research and Development Vancouver Design Center 480 image refreshed by the S1D13743 Hardware Functional Specification Issue Date: 2010/05/18 ...
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... Epson Research and Development Vancouver Design Center 18.3 180° SwivelView The following figure shows how the programmer sees a 480x320 landscape image and how the image is being displayed. The application image is written to the S1D13743 in the following sense: A–B–C–D. The display is refreshed in the following sense: D-C-B-A. ...
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... REG[34h] bits 1-0). All Start Addresses and Line Offsets are automatically calculated by hardware. S1D13743 X70A-A-001-02 B display start address (panel origin) Revision 2.7 Epson Research and Development Vancouver Design Center 480 image refreshed by the S1D13743 Hardware Functional Specification Issue Date: 2010/05/18 ...
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... Epson Research and Development Vancouver Design Center 19 Host Interface 19.1 Using the Intel 80 Interface Accessing the S1D13743 through the Intel 80 host interface is a multiple step process. All Registers and Memory are accessed through the register space. Note All Register accesses are 8-bit only, except for the Memory Data Port. If the Host interface is 16-bits wide (CNF1 = 1b), the lsbs (MD[7:0]) are used for all registers except the Memory Data Port ...
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... Additional data writes can be performed as the register addresses will be auto-incre- mented. MD[7:0] Figure 19-1: Register Write Example Procedure S1D13743 X70A-A-001-02 CS# D/C# RD# WE# Address Data Data bits 7-0 Write Write Write Revision 2.7 Epson Research and Development Vancouver Design Center Data Write 4 Hardware Functional Specification Issue Date: 2010/05/18 ...
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... Epson Research and Development Vancouver Design Center 19.1.2 Register Read Procedure 1. Perform an address write to setup register address bits 7-0. 2. Perform a data read to get the register value. 3. Additional data reads can be performed as the register addresses will be auto-incre- mented. MD[7:0] MD[7:0] Figure 19-2: Register Read Example Procedure ...
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... The Memory Data Port Register is located in the 9th register address after the Window X Start Position. Writes to the Memory Data Port will auto-increment the internal memory address only. S1D13743 X70A-A-001-02 Epson Research and Development Revision 2.7 Vancouver Design Center Hardware Functional Specification Issue Date: 2010/05/18 ...
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... Epson Research and Development Vancouver Design Center Figure 19-3: Sequential Memory Write Example Hardware Functional Specification Issue Date: 2010/05/18 Revision 2.7 Page 103 S1D13743 X70A-A-001-02 ...
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... Note To access the 8 lsb’s for each 24-bit value, you must know the physical address as they are stored at different locations as compared to the upper 16-bits. S1D13743 X70A-A-001-02 Epson Research and Development Revision 2.7 Vancouver Design Center Hardware Functional Specification Issue Date: 2010/05/18 ...
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... Epson Research and Development Vancouver Design Center 20 Double Buffering 20.1 Double Buffer Controller Double buffering is provided to prevent tearing of streaming video data. All static (non- video) image data will always be written to the upper half (Buffer 1) of the frame buffer. When video is being input, the first frame will be written to the lower half (Buffer 2) of the double buffer ...
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... The static image data from Buffer 1 is sent to the LCD, but the video window comes from Buffer 2. Figure 20-2: Double Buffer Example Revision 2.7 Epson Research and Development Vancouver Design Center Buffer 1 Input PIP Background Output ...
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... Epson Research and Development Vancouver Design Center 20.2 Double Buffering Limitations There are some limitations to double buffering: • Consider the case where there is a video stream being input and the user wants to place a static PIP over all or some part of the video window. The user can write the PIP, but when the video stream is continued, it will destructively overwrite the PIP, so that it will appear as though the PIP is under the video window ...
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... Pin Number Pin Name D9 D10 D11 PCLK C11 J8, J9, J10, J11, K4, K5, R5, R4, R3, R2, R1, R0, K6, K7, K8, K9, K10, L3, G5, G4, G3, G2, G1, G0, L4, L5, L6, L7, L8, L9 B5, B4, B3, B2, B1, B0 Revision 2.7 Epson Research and Development Vancouver Design Center Hardware Functional Specification Issue Date: 2010/05/18 ...
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... Epson Research and Development Vancouver Design Center 21.1.2 S1D13743 Register Settings for 352x416 TFT Panel Note The registers listed below are only those associated with panel specific timing issues All other registers are not shown here. Note When a window is setup for YUV data, the data must always alternate between odd and even lines, starting with an odd line ...
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... PLL is used to generate SYSCLK. Actual settings can vary and still remain within the LCD panel timing requirements. S1D13743 X70A-A-001-02 Value 9Fh Window Y End Position = 415 01h Revision 2.7 Epson Research and Development Vancouver Design Center Comment Hardware Functional Specification Issue Date: 2010/05/18 ...
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... Epson Research and Development Vancouver Design Center 21.2 Host Bus Timing D/C# ½IOVDD CS# WE# ½IOVDD MD[15:0] write RD# MD[15:0] read Note: The D/C# input pin is used to distinguish between Address and Data. Note: The register address will auto-increment in word increments for all register access except the Gamma Correction Table Data register and Memory Data Port ...
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... S1D13743 X70A-A-001-02 Parameter 0.6 + twrl 1.3 + trdl Note 1 122.1 + trdh 108.1 + trdh Note 2 122.1 108 Revision 2.7 Epson Research and Development Vancouver Design Center Min Max Unit Description 1.4 — ns 0.3 — ns — ns — ns 9.2 — ...
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... Epson Research and Development Vancouver Design Center 21.3 Panel Timing t10 t11 PCLK REG[28h] bit 7=1 t9 t10 t11 PCLK REG[28h] bit 7=0 VD[17:0] Hardware Functional Specification Issue Date: 2010/05/ t12 t12 invalid Note: 1 pixel/clock Mode Figure 21-2: 18-Bit TFT A.C. Timing Revision 2 ...
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... Initialize the registers to the default state by ' running the register list generated by 13743CFG '---------------------------------------------------------- init ' Set the window to the full screen and clear the display '---------------------------------------------------------- SetWin.txt S1D13743 X70A-A-001-02 Parameter Revision 2.7 Epson Research and Development Vancouver Design Center Min Typ Max — 15.54 — — 73.67 — ...
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... Epson Research and Development Vancouver Design Center f WIN 0 ' ROTATE 0 '---------------------------------------------------------- print "Color bars at SwivelView 0\n" DrawBarsA.txt Pause.txt ' ROTATE 90 ' NOTE: There is a bug with the Fill WINdow command in ' Play which causes the 90 and 270 degree fills ' to be filled incorrectly. This will be corrected. '---------------------------------------------------------- print " ...
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... SetWin.txt $StartX $StartY $EndX $EndY f WIN $Color set $StartY ($StartY + $Lines) set $EndY ($EndY + $Lines) set $Color ($Color + 0821) set $Bars ($Bars - 1) if $Bars!=0 then goto LOOP S1D13743 X70A-A-001-02 Epson Research and Development Revision 2.7 Vancouver Design Center Hardware Functional Specification Issue Date: 2010/05/18 ...
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... Epson Research and Development Vancouver Design Center DrawBarsB.txt verbose cmd:off out:on set:off '============================================================================== ' DrawBarsB.txt - Play script for the 13743 ' ' This script draws horizontal bars in SwivelView 90 and SwivelView 270 ' display modes. '============================================================================== set $Height (reg[16 set $Lines ($Height / 8) set $StartX 0 set $StartY 0 set $EndX ...
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... LOOP Pause.txt verbose cmd:off out:on set:off halt 0 print "Paused . . . press any key to continue\n" input line S1D13743 X70A-A-001-02 $Width $Lines Revision 2.7 Epson Research and Development Vancouver Design Center Hardware Functional Specification Issue Date: 2010/05/18 ...
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... Epson Research and Development Vancouver Design Center SetWin.txt verbose cmd:off out:on set:off '------------------------------------------------------------------------------ ' SetWin.txt - Play script for the 13743 ' ' This script is functionally identical to the Play command 'win'. Call this ' script to set the 13743 window co-ordinates as specified by the arguments Syntax: SetWin Where Left edge window X position ...
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... S1D13743 X70A-A-001-02 Optional, but recommended To Digital IOV Plane Digital V Plane SS Figure 22-1: PLL Power Layout Revision 2.7 Epson Research and Development Vancouver Design Center PLLV DD C1 S1D13743 PLLV SS Typical Values: L1, L2 isolation bead C1 ~10uf bypass C2 1nf bypass C3 ...
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... Epson Research and Development Vancouver Design Center • Place the ferrite beads (L1 and L2) parallel to each other with minimal clearance between them. Both bypass caps (C2 and C3) should be as close as possible to the inductors. The traces from C3 to the power planes should be short parallel traces on the same side of the board with just the normal small clearance between them ...
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... Page 122 23 Mechanical Data TOP VIEW A1 corner SIDE VIEW BOTTOM VIEW A1 corner Figure 23-1: S1D13743 FCBGA 121-pin Package S1D13743 X70A-A-001-02 ±0.20 8.0 Die Size 0. 1011 Revision 2.7 Epson Research and Development Vancouver Design Center 0.75 units = mm Hardware Functional Specification Issue Date: 2010/05/18 ...
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... Epson Research and Development Vancouver Design Center 109 144 A 2 Symbol max θ Figure 23-2: S1D13743 QFP20 144-pin Package Hardware Functional Specification Issue Date: 2010/05/ 108 INDEX Dimension in Millimeters Min Nom Max — 20 — — 20 — — 22 — — 22 — — ...
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... Device Name Die Revision Code Package Type Process and Package Revision Code [Blank] Control Code Year of Manufacture Month of Manufacture W/F Lot No. JAPAN Figure 23-3: S1D13743 FCBGA 121-pin Package Marking S1D13743 X70A-A-001-02 Epson Research and Development Y Package Center Line 2.78 1. 0.74 Y’ ...
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... Epson Research and Development Vancouver Design Center Y X X’ Pin 1 Y’ (1) 2.0 (7) ( Package Center Line Item Logo Specified JAPAN Device Name Control Code Year of Manufacture Week of Manufacture W/F Lot No. Figure 23-4: S1D13743 QFP 144-pin Package Marking Hardware Functional Specification Issue Date: 2010/05/18 ...
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... The following documents contain additional information related to the S1D13743. Document numbers are listed in parenthesis after the document name. All documents can be found at the Epson Research and Development Website at www.erd.epson.com. • S1D13743 Product Brief (X70A-C-001-xx) • S5U13743P00C100 Evaluation Board User Manual (X70A-G-001-xx) ...
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... EPSON EUROPE ELECTRONICS GmbH Riesstrasse 15, 80992 Munich, GERMANY Phone: +49-89-14005-0 FAX: +49-89-14005-110 25.1 Ordering Information To order the S1D13743 Mobile Graphics Engine, contact the Epson sales representative in your area. Hardware Functional Specification Issue Date: 2010/05/18 ASIA EPSON (CHINA) CO., LTD. 7F, Jinbao Bldg., No.89 Jinbao St., ...
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... Setting SYSCLK and PCLK - remove “5 x 9.5” from “For example, if the...” • section Figure 23-1, change Side View ball height to 0.23mm • section 26 Sales and Technical Support - changes to Epson offices and addresses X70A-A-001-02 Revision 2.5 - Issued: 2008/05/07 • ...
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... X70A-A-001-02 Revision 2.01 (Issued 2006/04/28) • all changes from the last revision of the spec are highlighted in Red • updated EPSON tagline • section 4.2.1 Intel 80 Host Interface - for GPIO_INT add reference to General Purpose IO Pins Registers to pin description. • section 4.2.4 Miscellaneous - for GPIO[7:0] rewrite pin description, for PWRSVE rewrite pin description for no pull-down resistor • ...
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... Setting SYSCLK and PCLK - change first equation to “ 0.976) x 0.485ns” from “14.94ns < T BBC S1D13743 X70A-A-001-02 Epson Research and Development out to separate power types (P Total CORE < (T SYSCLK BBC Revision 2.7 ...
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... Epson Research and Development Vancouver Design Center • REG[04h] - change register name from “PLL M-Divider Register 0” to “PLL M-Divider Register” • REG[18h] - change minimum register value in note to 3 • REG[2Ah] - add note “For YUV 4:2:2 and YUV 4:2:0 settings, the width...” ...
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... Intel 80, 16-bit Interface Color Formats diagrams to use the proper 13743 pin names • section 13, updated the YUV Timing diagrams to use the proper 13743 pin names • section 14, added data input to LUT S1D13743 X70A-A-001-02 Epson Research and Development Revision 2.7 Vancouver Design Center Hardware Functional Specification Issue Date: 2010/05/18 ...
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... Epson Research and Development Vancouver Design Center • section 14.1, reworded some of the steps in the Gamma Correction Programming Example • section 17, minor wording changes to clarify the Host Interface usage examples X70A-A-001-00 Revision 0.05 • section 7.1.1 Input Clocks - Table 7-1 Clock Input Requirements (CLKI) - change Input clock frequency - PLL max to 66 ...
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... Page 134 X70A-A-001-00 Revision 0.01 • initial draft of the S1D13743 specification S1D13743 X70A-A-001-02 Epson Research and Development Revision 2.7 Vancouver Design Center Hardware Functional Specification Issue Date: 2010/05/18 ...