V2DIP1-64 FTDI, V2DIP1-64 Datasheet - Page 15

• Manufacturer Part Number: V2DIP1-64
• Description: Interface Modules & Development Tools USB Vinculum-II 64 Pin Mod 1 USB Port
• Manufacturer: FTDI

Specifications of V2DIP1-64

• Interface Type: USB, Serial, UART, FIFO, SPI
• Data Bus Width: Serial, 8 bit
• Operating Supply Voltage: 5 V
• Product: Interface Modules
• For Use With/related Products: VNC2-64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

23, J1-3, J1-7, J2-8, J2-4
J2-17, J1-14, J1-18, J1-26, J1-30, J2-
27, J2-22, J1-4, J1-8, J2-7, J2-3
J2-16, J1-15, J1-20, J1-27, J2-30, J2-
26, J1-1, J1-5, J1-9, J2-6, J2-2
J2-15, JI-16, J1-21, J1-28, J2-29, J2-24,
J1-2, J1-6, J2-9, J2-5, J2-1
23, J1-3, J1-7, J2-8, J2-4
J2-17, J1-14, J1-18, J1-26, J1-30, J2-
27, J2-22, J1-4, J1-8, J2-7, J2-3
J2-16, J1-15, J1-20, J1-27, J2-30, J2-
26, J1-1, J1-5, J1-9, J2-6, J2-2
J2-15, JI-16, J1-21, J1-28, J2-29, J2-24,
J1-2, J1-6, J2-9, J2-5, J2-1
23, J1-3, J1-7, J2-8, J2-4
J2-17, J1-14, J1-18, J1-26, J1-30, J2-
27, J2-22, J1-4, J1-8, J2-7, J2-3
J2-16, J1-15, J1-20, J1-27, J2-30, J2-
26, J1-1, J1-5, J1-9, J2-6, J2-2
J2-15, JI-16, J1-21, J1-28, J2-29, J2-24,
J1-2, J1-6, J2-9, J2-5, J2-1
Table 3.6 - Data and Control Bus Signal Mode Options – Parallel FIFO Interface
shows the Parallel FIFO Interface signals and the pins that they can be mapped.
J2-14, J1-17, J1-24, J1-29, J2-28, J2-
J2-14, J1-17, J1-24, J1-29, J2-28, J2-
J2-14, J1-17, J1-24, J1-29, J2-28, J2-
Available Pins
Copyright © 2010 Future Technology Devices International Limited
fifo_data[0]
fifo_data[1]
fifo_data[2]
fifo_data[3]
fifo_data[4]
fifo_data[5]
fifo_data[6]
fifo_data[7]
fifo_txe#
fifo_rxf#
fifo_wr#
fifo_rd#
V2DIP1-64 VNCL2-64Q Development Module Datasheet Version 1.0
Name
Output
Output
Type
Input
Input
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
When high, do not read data
from the FIFO. When low, there
is data available in the FIFO
which can be read by strobing
RD# low, then high.
When high, do not write data into
the FIFO. When low, data can be
written into the FIFO by strobing
fifo_wr# high, then low.
Enables the current FIFO data
byte on D0...D7 when low.
Fetches the next FIFO data byte
(if available) from the receive
FIFO buffer when fifo_rd# goes
from high to low
Writes the data byte on the
D0...D7 pins into the transmit
FIFO buffer when fifo_wr# goes
from high to low.
Document Reference No.: FT_000165
FIFO data bus Bit 0
FIFO data bus Bit 1
FIFO data bus Bit 2
FIFO data bus Bit 3
FIFO data bus Bit 4
FIFO data bus Bit 5
FIFO data bus Bit 6
FIFO data bus Bit 7
Description
Clearance No.: FTDI# 154
14