LFXP2-5E-B-EVN Lattice, LFXP2-5E-B-EVN Datasheet
LFXP2-5E-B-EVN
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LFXP2-5E-B-EVN Summary of contents
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... LatticeXP2 Brevia Development Kit User’s Guide June 2010 Revision: EB53_01.1 ...
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... Note: Static electricity can severely shorten the life span of electronic components. Features The LatticeXP2 Brevia Development Kit includes: • LatticeXP2 Brevia Evaluation Board – This is a small board (about the size of a business card) with the follow- ing on-board components and circuits: – LatticeXP2-5E 6TN144C – ...
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... Figure 1. LatticeXP2 Brevia Evaluation Board, Top Side RS232 Power LED LatticeXP2 Device This board features a LatticeXP2 FPGA with a 1.2V core supply. It can accommodate all pin-compatible LatticeXP2 devices in the 144-pin TQFP (20x20 mm) package. A complete description of this device can be found in the LatticeXP2 Family Data Sheet. Demonstration Design Lattice provides a demo that illustrates key applications of the LatticeXP2 device ...
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... LatticeXP2 Brevia Evaluation Board necessary to start and configure a VT100 or ANSI style terminal emulator program like HyperTerminal (Windows) or Minicom (Linux). The RS232 port on the LatticeXP2 Brevia Evaluation Board is configured to operate at 115.2Kbps, 8 data bits, 1 stop bit, and no parity, and no flow control. Once the terminal emulator is running on the host computer, and the RS232 cable is attached between the host computer and the LatticeXP2 Brevia Evaluation Board you will see the following banner displayed when the board is powered, or following a RESET button assertion ...
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... SRAM location. Read SPI Flash Memory IDCode Command The SPI ROM device on the LatticeXP2 Brevia Evaluation Board can be queried and will return the ID code imple- mented by the ROM manufacturer. The LatticeMico8 initiates memory transactions using the SPI Memory control- ler to acquire the data ...
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... Lattice Semiconductor Read DIP Switch Bank The LatticeMico8 has the ability to read the state of switches 1-4 on the DIP switch bank. The pushbutton switches are can also be read. Each pushbutton press toggles the internal state of a register in the FPGA. The current state of the register is displayed on the high nibble of the output ...
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... From the terminal window press 8. Example: Please Enter the Address(18 bits,Hex), eg: 1f26a, no Spaces, then Press ENTER: 10000 Please Enter the Data(8 bits,Hex), eg: b7, no Spaces, then Press ENTER: 93 SPI Write Done. LatticeXP2 Brevia Development Kit 7 User’s Guide ...
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... Starting SPI Auto-Test.......................................................... ...................................................................... SPI Test Done: Successful. Download Demo Designs Lattice distributes source and programming files for a variety of demonstration designs compatible with the LatticeXP2 Brevia Evaluation Board. To download demo designs: 1. Browse to the LatticeXP2 Brevia Development Kit web page tions download and save the file ...
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... Lattice Semiconductor 2. Extract the contents of Demo_LatticeXP2_Brevia_Soc_vhdl.zip and Demo_LatticeXP2_Brevia_Soc_verilog.zip to an accessible location on your hard drive. One or more designs will be extracted and each will follow the following basic form. Demo Demo1 Where: • \project – ispLEVER project (.syn), preferences (.lpf), and programming file (.jed). This directory may contain intermediate results of the ispLEVER build process. • ...
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... Choose ispTools > Scan Chain. The New Scan Configuration Setup window appears. The LatticeXP2 appears in the device list as LFXP2-5E. 11. Right-click the LFXP2-5E entry and choose Edit Device... The Device Information dialog appears. 12. From the Data File section, click the Browse button. The Open Data File dialog appears. ...
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... Browse to the <Demo Dir>\project folder, select <Demo>.jed, and click Open. From the Operation list choose Flash Erase, Program, Verify and click OK. 14. Choose Project > Download. ispVM reprograms the LatticeXP2 Brevia Evaluation Board. A progress bar with a small timer window will appear to show elapsed programming time. At the end of pro- gramming, the configuration setup window’ ...
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... Figure 3. LatticeXP2 Brevia Evaluation Board Block Diagram 31 2x20 Header 8 2x5 Header 4 SPI Flash 1 Mbit SRAM Header Code. GPIO SPI LatticeXP2 LFXP2-5E-6TN144C 28 JTAG Programming 2x5 12 LatticeXP2 Brevia Development Kit User’s Guide Push-button (x4) GSRN/IO Push-button 4 4-Bit DIP Switch 8 8 LEDs ...
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... Pin Name Pin Number 3.3V 3.3V EXP_IO15 EXP_IO31 EXP_IO14 EXP_IO30 EXP_IO13 EXP_IO29 EXP_IO12 EXP_IO28 EXP_IO11 EXP_IO27 GND GND EXP_IO10 13 LatticeXP2 Brevia Development Kit User’s Guide FPGA FPGA Pin Number Pin Name Functionality NC NC RS232_Rx_TTL Receive RS232_Tx_TTL Transmit NC NC Ground Ground ...
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... EXP_IO2 EXP_IO18 EXP_IO1 EXP_IO17 GND GND XP2_RESET EXP_IO16 Expansion Connector Pin Name EXP_IO36 3.3V EXP_IO37 EXP_IO32 EXP_IO38 EXP_IO33 EXP_IO39 EXP_IO34 GND EXP_IO35 14 LatticeXP2 Brevia Development Kit User’s Guide FPGA Pin Number Pin Functionality 116 96 115 94 114 93 113 92 78 Ground Ground ...
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... Eight LEDs, four pushbutton switches and one DIP (4) switch are provided. Table 4. LED Interface Table 5. Switch Interface Flash Interface The LatticeXP2 Brevia Evaluation Board provides 4Mbits of non-volatile flash memory. The Flash uses the four- wire SPI communication interface. Table 6. Flash Interface LED FPGA Pin Number ...
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... Lattice Semiconductor SRAM Interface The LatticeXP2 Brevia Evaluation Board provides 1Mbit of asynchronous SRAM memory in a 128K x 8-bit configu- ration. Table 7. SRAM Interface Configuration Interface Jumper 5 controls the XP2 CFG0 input control pin. Table 8. Configuration Interface The factory default setting leave it unshunted. CFG0 has a weak pullup resistor. ...
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... FPGA The Lattice XP2 Brevia board is based on the Lattice Semiconductor LatticeXP2 non-volatile FPGA. The board is populated with a 5K LUT device in a 144 TQFP package. A complete description of the device can be found in the LatticeXP2 Family Data Sheet and on the JTAG Cable Color Coding Table 10 ...
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... A final option is to use ispVM System to read the current bitstream in the FPGA, and then to reprogram the FPGA with your desired bitstream. Ordering Information Description LatticeXP2 Brevia Development Kit LatticeXP2 Brevia Development Kit China RoHS Environment-Friendly Ordering Part Number LFXP2-5E-B-EVN 18 User’s Guide Use Period (EFUP) ...
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... June 2010 (c) 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The speci• cations and information herein are subject to change without notice. ...
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... Lattice Semiconductor Appendix A. Schematics Figure 4. LatticeXP2 Brevia Evaluation Board Block Diagram LatticeXP2 Brevia Development Kit 20 User’s Guide ...
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... Lattice Semiconductor Figure 5. SPI Flash, SRAM, LEDs and Switches LatticeXP2 Brevia Development Kit 21 User’s Guide ...
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... Lattice Semiconductor Figure 6. Banks 6 and 7 LatticeXP2 Brevia Development Kit 22 User’s Guide ...
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... Lattice Semiconductor Figure 7. Banks 0-5 LatticeXP2 Brevia Development Kit 23 User’s Guide ...
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... Lattice Semiconductor Figure 8. Power LatticeXP2 Brevia Development Kit 24 User’s Guide ...
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... PHONEJACK CON_DC006_PWRJACK 330E RC0402 2k2 RC0402 0 RC0402 10K RC0402 0E RC0402 121E RC0402 240E RC0402 390E RC0402 SW_SPST_4 SW_DIP8 SW KEY-YM061 SW_B3FS-1000P XP2 Reset SW_B3FS-1000P SST25VF020-20-4C-SAE SOIC127P600_8 BS62LV1027SC-70 SOIC127P1400_32 ST3232/SO SOIC127P780_16 LFXP2-5E-T144/TN144 TQFP50P2200X2200_144 LM1117A SOT223 3SWO50. crystal oscillator 25 User’s Guide PCB Footprint ...