4313-T-B1_B_ANY Silicon Laboratories Inc, 4313-T-B1_B_ANY Datasheet
4313-T-B1_B_ANY
Specifications of 4313-T-B1_B_ANY
Related parts for 4313-T-B1_B_ANY
4313-T-B1_B_ANY Summary of contents
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... MCU allowing for extended MCU sleep periods. Additional features, such as an automatic wake-up timer, 64-byte RX FIFO, and a preamble detection circuit, are available. The Si4313's digital receive architecture features an ADC and DSP based modem that performs the radio demodulation and filtering for increased performance. ...
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... Si4313-B1 Functional Block Diagram 2 Rev. 1.0 ...
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... Auxiliary Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.1. Smart Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 8.2. Microcontroller Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 8.3. Low Battery Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 8.4. Wake-Up Timer and 32 kHz Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.5. GPIO Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.6. RSSI and Clear Channel Assessment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9. Reference Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 10. Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10.1. RX LNA Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Rev. 1.0 Si4313-B1 Page 3 ...
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... Si4313-B1 11. Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 12. Pin Descriptions: Si4313 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 13. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 14. Package Outline: Si4313- 15. Landing Pattern: 20-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 16. Top Marking: 20-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 16.1. Top Mark Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 4 Rev. 1.0 ...
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... Figure 9. FIFO Threshold .......................................................................................................... 29 Figure 10. POR Glitch Parameters............................................................................................ 32 Figure 11. WUT Interrupt and WUT Operation.......................................................................... 37 Figure 12. RSSI Value vs. Input Power..................................................................................... 39 Figure 13. Reference Test Card................................................................................................ 40 Figure 14. 20-Pin Quad Flat No-Lead (QFN) ............................................................................45 Figure 15. 20-Pin QFN Landing Pattern.................................................................................... 46 Figure 16. Si4313 Top Marking .................................................................................................48 Rev. 1.0 Si4313-B1 Page 5 ...
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... Si4313- ABLES Table 1 Table 1. DC Characteristics ......................................................................................................7 Table 2. Synthesizer AC Electrical Characteristics Table 3. Receiver AC Electrical Characteristics Table 4. Auxiliary Block Specifications Table 5. Digital IO Specifications (SDO, SDI, SCLK, nSEL, and nIRQ) Table 6. GPIO Specifications (GPIO_0, GPIO_1 and GPIO_2) ............................................... 12 Table 7. Absolute Maximum Ratings ........................................................................................ 13 Table 8. Operating Modes ........................................................................................................16 Table 9 ...
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... Production Test Conditions" on page 14. 2. Guaranteed by qualification. Qualification test conditions are listed in "1.1.1. Production Test Conditions" on page 14. Conditions 2 Digital Regulator OFF Low Power Digital Regulator ON (Register values retained) OFF Synthesizer and regulators enabled Rev. 1.0 Si4313-B1 Min Typ Max Units 1.8 3.0 3.6 V — ...
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... Si4313-B1 Table 2. Synthesizer AC Electrical Characteristics Parameter Symbol Synthesizer F SYNTH-LB Frequency F Range SYNTH-HB Synthesizer F RES-LB Frequency F 2 Resolution RES-HB When using external reference signal driving Reference f Frequency REF_LV 2 crystal. Measured peak-to-peak (V Input Level Measured from leaving Ready mode with Synthesizer t XOSC running to any frequency including ...
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... GFSK with BT = 0.5, channel spacing = 150 kHz Desired Ref Signal 3 dB above sensitivity. Interferer and desired modulated with 40 kbps kHz GFSK with 937 kHz Rev. 1.0 Si4313-B1 Min Typ Max Units 240 — 960 MHz — –118 — ...
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... Si4313-B1 Table 4. Auxiliary Block Specifications Parameter Symbol Low Battery Detector LBD 2 RES Resolution Low Battery Detector LBD 2 CT Conversion Time Microcontroller Clock F MC Output Frequency 30 MHz XTAL t 30M Start-Up time 30 MHz XTAL 30M 2 RES Cap Resolution 32 kHz XTAL t 2 32k Start-Up Time ...
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... Guaranteed by qualification. Qualification test conditions are listed in "1.1.1. Production Test Conditions" on page 14. Conditions 0<V < <1 mA source 1 <1 mA sink 1 Rev. 1.0 Si4313-B1 1 Min Typ Max Units — — — — — — –0.6 — — — — 0.6 V –100 — 100 nA –0.6 — ...
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... Si4313-B1 Table 6. GPIO Specifications (GPIO_0, GPIO_1 and GPIO_2) Parameter Symbol 2 Rise Time T RISE 2 Fall Time T FALL 2 Input Capacitance C IN Logic High Level Input Voltage Logic Low Level Input Voltage 2 Input Current I IN Input Current I 2 INP if pull-up activated I OMAXLL I Maximum OMAXLH ...
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... Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This is an ESD-sensitive device. Value –0.3, +3.6 –0.3, V +0.3 DD –0.3, V +0.3 DD +10 –40 to +85 30 +125 –55 to +125 Rev. 1.0 Si4313-B1 Unit dBm °C °C/W °C °C 13 ...
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... All RF input levels refer to the pins of the Si4313 (not the RF module). 1.1.2. Qualification Test Conditions TA = –40 to +85 °C. VDD = +1.8 to +3.6 VDC. Based upon standard reference design test cards. All RF input levels refer to the pins of the Si4313 (not the RF module). 14 Rev. 1.0 ...
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... Gaussian filtering at any frequency between 240–960 MHz. The Si4313 is designed to work with a microcontroller, crystal, and a few passives to create a very low-cost system. Voltage regulators are integrated on-chip, which allows for a wide range of operating supply voltage conditions from +1 ...
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... Si4313-B1 2.2. Operating Modes The Si4313 provides several operating modes, which can be used to optimize the power consumption of the receive application. Depending upon the system communication protocol, an optimal trade-off between radio wake time and power consumption can be achieved. In general, any given operating mode may be classified as an Active mode or a Power Saving mode. Table 8 indicates which blocks are enabled (active) in each corresponding mode. With the exception of the Shutdown mode, all can be dynamically selected by sending the appropriate commands over the SPI. An " ...
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... Select high period SW To read back data from the Si4313, the R/W bit must be set to 0 followed by the 7-bit address of the register from which to read. The 8 bit DATA field following the 7-bit ADDR field is ignored on the SDI pin when R The next eight negative edge transitions of the SCLK signal will clock out the contents of the selected register ...
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... ADDR and read from/write to the next address. An example burst write transaction is shown in Figure 4, and a burst read is shown in Figure 5. As long as nSEL is held low, input data will be latched into the Si4313 every eight SCLK cycles. First Bit ...
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... Mode and Function Control 1". Table 10 shows each of the operating modes with the time required to reach RX mode as well as the current consumption of each mode. The Si4313 includes a low-power digital regulated supply (LPLDO), which is internally connected in parallel to the output of the main digital regulator (and is available externally at the VR_DIG pin); this common digital supply voltage is connected to all digital circuit blocks, including the digital modem, crystal oscillator, SPI, and register space. The LPLDO has extremely low quiescent current consumption but limited current supply capability ...
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... Si4313-B1 3.2.1. SHUTDOWN State The SHUTDOWN state is the lowest current consumption state of the device with nominally less than current consumption. The shutdown state may be entered by driving the SDN pin (Pin 20) high. The SDN pin should be held low in all states except the SHUTDOWN state. In the SHUTDOWN state, the contents of the registers are lost and there is no SPI access ...
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... The operational status of the Si4313 can be read from the Device Status register, 'Register 02h' 3.3. Interrupts The Si4313 is capable of generating an interrupt signal when certain events occur. The chip notifies the microcontroller that an interrupt event has occurred by setting the nIRQ output pin LOW = 0. This interrupt signal will be generated when any one (or more) of the interrupt events (corresponding to the Interrupt Status bits) shown below occur ...
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... Si4313-B1 3.4. System Timing The VCO will automatically calibrate at every frequency change or power-up. The PLL T0 time is to allow for bias settling of the VCO. The PLL TS time is for the settling time of the PLL, which has a default setting of 100 µs. The total time for PLL T0, PLL CAL, and PLL TS under all conditions is 200 µs. In certain applications, the PLL T0 time and the PLL CAL may be skipped for faster turnaround time ...
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... When the AFC loop is enabled, its pull-in-range is determined by the bandwidth limiter value 156.25 Hz hbsel Desired Offset --------------------------------------------------------------- - = 156.25 Hz hbsel fo[7] fo[6] fo[5] fo[4] fo[3] Rsvd Rsvd Rsvd Rsvd Rsvd Rev. 1.0 Si4313-B1 POR Def fo[2] fo[1] fo[0] 00h Rsvd fo[9] fo[8] 00h 23 ...
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... Si4313-B1 (AFCLimiter) which is located in register 2Ah. AFC_pull_in_range = ±AFCLimiter[7:0] x (hbsel+1) x 625 Hz The AFC Limiter register is an unsigned register and its value can be obtained from the EZRadioPRO Register Calculator spreadsheet or from WDS. The amount of error correction feedback to the Fractional-N PLL before the preamble is detected is controlled from afcgearh[2:0] ...
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... All modulation options are programmed in "Register 71h. Modulation Mode Control 2." 4.1. Modulation Type The Si4313 can be configured to support three alternative modulation options: Gaussian Frequency Shift Keying (GFSK), Frequency Shift Keying (FSK), and On-Off Keying (OOK). The type of modulation is selected with the modtyp[1:0] bits in " ...
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... Si4313-B1 5. Internal Functional Blocks This section provides an overview of some of the key blocks of the internal radio architecture. 5.1. RX LNA The input frequency range for the LNA is 240–960 MHz. The LNA provides gain with a noise figure low enough to suppress the noise of the following stages. The LNA has one step of gain control that is controlled by the analog gain control (AGC) algorithm ...
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... VCO calibration may be skipped by setting the appropriate register. 5.7. Crystal Oscillator The Si4313 includes an integrated 30 MHz crystal oscillator with a fast start-up time of less than 600 µs when a suitable parallel resonant crystal is used. The design is differential with the required crystal load capacitance integrated on-chip to minimize the number of external components ...
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... BOM cost is reduced. The available clock frequencies and GPIO configuration are discussed further in "8.2. Microcontroller Clock" on page 33. The Si4313 may also be driven with an external 30 MHz clock signal through the XOUT pin. When driving with an external reference or using a TCXO, the XTAL load capacitance register should be set to 0. ...
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... Interrupt Status registers. Figure 9. FIFO Threshold rxmpk Reserved Rev. 1.0 Si4313- POR Def enldm ffclrrx Reserved 00h rxafthr[0] 37h ...
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... Si4313-B1 6.2. Preamble Length The preamble detection threshold determines the number of valid preamble bits the radio must receive to qualify a valid preamble. The preamble threshold should be adjusted depending on the nature of the application. The required preamble length threshold will depend on when receive mode is entered in relation to the start of the transmitted packet and the length of the transmit preamble ...
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... An application note is available to describe how to use the calculator and to provide advanced descriptions of the modem settings and calculations via registers 1C-25h. The modulation index is equal to twice the peak deviation divided by the data rate (Rb). http://www.silabs.com Rev. 1.0 Si4313- the CD 31 ...
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... Auxiliary Functions 8.1. Smart Reset The Si4313 contains an enhanced integrated SMART RESET or POR circuit. The POR circuit contains both a classic level threshold reset as well as a slope detector, POR. This reset circuit was designed to produce a reliable reset signal under any circumstances. Reset will be initiated if any of the following conditions occurs: Initial power on, VDD starts from GND: reset is active till VDD reaches VRR (see table). ...
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... If the microcontroller clock option is being used, there may be a need for a system clock for the microcontroller while the Si4313 is in SLEEP mode. Since the crystal oscillator is disabled in SLEEP mode in order to save current, the low-power 32.768 kHz clock can be automatically switched to become the microcontroller clock. This feature is called enable low frequency clock and is enabled by the enlfc bit in Register 0Ah ...
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... Si4313-B1 Another available feature for the microcontroller clock is the clock tail, clkt[1:0] in Register 0Ah. Microcontroller Output Clock. If the low frequency clock feature is not enabled (enlfc = 0), the system clock to the microcontroller is disabled in SLEEP mode. However, it may be useful to provide a few extra cycles for the microcontroller to complete its operation prior to the shutdown of the system clock signal ...
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... Table 15. LBD ADC Range ADC Value VDD Voltage [V] 0 <1.7 1 1.7–1.75 2 1.75–1.8 — — 29 3.1–3.15 30 3.15–3.2 31 >3.2 Rev. 1.0 Si4313-B1 35 ...
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... Si4313-B1 8.4. Wake-Up Timer and 32 kHz Clock Source The chip contains an integrated wake-up timer which can be used to periodically wake the chip from SLEEP mode. The wake-up timer runs from the internal 32.768 kHz RC Oscillator. The wake-up timer can be configured to run when in SLEEP mode. If enwt = 1 in "Register 07h. Operating Mode and Function Control 1" when entering SLEEP mode, the wake-up timer will count for a time specified defined in Registers 14– ...
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... Current Consumption WUT Period GPIOX =00001 nIRQ SPI Interrupt Read Chip State Current Consumption Figure 11. WUT Interrupt and WUT Operation Interrupt Enable enwut =1 ( Reg 06h) Sleep Ready 1 Interrupt Enable enwut =0 ( Reg 06h) Sleep 1 uA Rev. 1.0 Si4313-B1 Sleep Ready Sleep 1 ...
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... Si4313-B1 8.5. GPIO Configuration Three general purpose IOs (GPIOs) are available. Numerous functions such as specific interrupts, TRSW control, microcontroller output, etc. can be routed to the GPIO pins as shown in the tables below. When in shutdown mode all the GPIO pads are pulled low. Note: The ADC should not be selected as an input to the GPIO in standby or sleep modes and will cause excess current con- sumption ...
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... Figure 12. RSSI Value vs. Input Power rssi[7] rssi[6] rssi[5] rssi[4] rssith[7] rssith[6] rssith[5] rssith[4] rssith[3] RSSI vs Input Power -80 -60 -40 In Pow [dBm] Rev. 1.0 Si4313- POR Def. rssi[3] rssi[2] rssi[1] rssi[0] — rssith[2] rssith[1] rssith[0] 00h - ...
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... Si4313-B1 9. Reference Design Reference designs, including recommended schematics, BOM, and layouts for many common applications, are available at www.silabs.com. 10. Customer Support Technical support for the complete family of Silicon Labs wireless products is available by accessing the wireless section of the Silicon Labs' website at www.silabs.com/wireless. For answers to common questions please visit the wireless Knowledge Base at www ...
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... Reserved Reserved rxncocomp crgain[7] crgain[6] crgain[5] crgain[4] rssi[7] rssi[6] rssi[5] rssi[4] rssith[7] rssith[6] rssith[5] rssith[4] Rev. 1.0 Si4313-B1 Data vc[3] vc[2] vc[1] Reserved Reserved cps[1] iext Reserved Reserved Reserved iwut ilbd ichiprdy enext Reserved Reserved Reserved ...
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... R/W Frequency Hopping Channel Select 7A R/W Frequency Hopping Step Size 7B 7E R/W RX FIFO Control 7F R/W FIFO Access Note: Detailed register descriptions are available in “AN589: Si4313 Detailed Register Descriptions.” 42 Table 16. Register Descriptions (Continued Afclim[7] Afclim[6] Afclim[5] Afclim[4] afc_corr[9] afc_corr[8] afc_corr[7] afc_corr[6] ...
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... PKG PADDLE_GND GND The exposed metal paddle on the bottom of the Si4313 supplies the RF and circuit ground(s) for the entire chip very important that a good solder connection is made between this exposed metal paddle and the ground plane of the PCB underlying the Si4313. ...
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... Si4313-B1 13. Ordering Information Part Number Si4313-B1-FM *Note: Add an (R) at the end of the device part number to denote tape and reel option; 2500 quantity per reel. 44 Description Package Type QFN-20 ISM Receiver Pb-free Rev. 1.0 Operating Temperature – °C ...
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... Package Outline: Si4313-B1 Figure 14 illustrates the package details for the Si4313-B1. Table 17 lists the values for the dimensions shown in the illustration. Figure 14. 20-Pin Quad Flat No-Lead (QFN) Symbol aaa bbb ccc ddd eee Notes: 1. All dimensions are shown in millimeters (mm) unless otherwise noted. ...
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... Si4313-B1 15. Landing Pattern: 20-Pin QFN Figure 15 shows the recommended landing pattern details for the Si4313- 20-Pin QFN package. Table 18 lists the values for the dimensions shown in the illustration. Figure 15. 20-Pin QFN Landing Pattern 46 Rev. 1.0 ...
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... A 2x2 array of 1.10 x 1.10 mm openings on 1.30 mm pitch should be used for the center ground pad. Card Assembly 8. A No-Clean, Type-3 solder paste is recommended. 9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for small body components. Rev. 1.0 Si4313-B1 Millimeters Max 4.00 4.00 0.50 REF 0.30 2 ...
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... X = Part Number Line 1 Marking Die Revision Line 2 Marking: TTTTT = Internal Code YY = Year Line 3 Marking Workweek 48 Figure 16. Si4313 Top Marking 0 = Si4313 B = Revision B1 Internal tracking code. Assigned by the Assembly House. Corresponds to the last significant digit of the year and workweek of the mold date. Rev. 1.0 ...
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... Updated "5.5. Digital Modem" on page 26. Updated "6.1. RX FIFO" on page 29. Deleted “Low Duty Cycle Mode” section. Deleted “Application Notes and Reference Material” section. Updated "11. Register Descriptions" on page 41. Updated "12. Pin Descriptions: Si4313" on page 43. Rev. 1.0 Si4313-B1 49 ...
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... Si4313- ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...