WM8974GEFL/V Wolfson Microelectronics, WM8974GEFL/V Datasheet - Page 18

Audio CODECs Mono Codec with Spkr

WM8974GEFL/V

Manufacturer Part Number
WM8974GEFL/V
Description
Audio CODECs Mono Codec with Spkr
Manufacturer
Wolfson Microelectronics
Datasheet

Specifications of WM8974GEFL/V

Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
QFN-24
Minimum Operating Temperature
- 25 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
WM8974
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Table 4 Input BOOST Stage Control
Table 5 Input BOOST Enable Control
MICROPHONE BIASING CIRCUIT
Table 6 Microphone Bias Enable
Table 7 Microphone Bias Voltage Control
The MICP path to the BOOST stage is controlled by the MICP2BOOSTVOL[2:0] register bits.
When MICP2BOOSTVOL=000 this input pin is completely disconnected from the BOOST stage.
Settings 001 through to 111 control the gain in 3dB steps from -12dB to +6dB.
The BOOST stage is enabled under control of the BOOSTEN register bit.
The MICBIAS output provides a low noise reference voltage suitable for biasing electret type
microphones and the associated external resistor biasing network. Refer to the Applications
Information section for recommended external components. The MICBIAS voltage can be altered via
the MBVSEL register bit.
MICBIAS=0.65*AVDD. The output can be enabled or disabled using the MICBEN control bit.
The internal MICBIAS circuitry is shown in Figure 9.
capability for MICBIAS is 3mA. The external biasing resistors therefore must be large enough to limit
the MICBIAS current to 3mA.
R47
Input BOOST
control
R2
Power
management 2
R1
Power management
1
R44
Input Control
REGISTER
REGISTER
ADDRESS
ADDRESS
REGISTER
REGISTER
ADDRESS
ADDRESS
2:0
6:4
4
BIT
BIT
4
8
BIT
BIT
AUX2BOOSTVOL
MICP2BOOSTVOL
BOOSTEN
LABEL
MICBEN
MBVSEL
LABEL
When MBVSEL=0, MICBIAS=0.9*AVDD and when MBVSEL=1,
LABEL
LABEL
0
0
0
DEFAULT
DEFAULT
DEFAULT
DEFAULT
000
000
Input BOOST enable
0 = Boost stage OFF
1 = Boost stage ON
Microphone Bias Enable
0 = OFF (high impedance output)
1 = ON
Microphone Bias Voltage Control
0 = 0.9 * AVDD
1 = 0.65 * AVDD
Controls the auxiliary amplifier to the input
boost stage:
000=Path disabled (disconnected)
001=-12dB gain through boost stage
010=-9dB gain through boost stage
111=+6dB gain through boost stage
Controls the MICP pin to the input boost stage
(NB, when using this path set
MICP2INPPGA=0):
000=Path disabled (disconnected)
001=-12dB gain through boost stage
010=-9dB gain through boost stage
111=+6dB gain through boost stage
Note that the maximum source current
PD, Rev 4.5, September 2008
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
Production Data
18

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