WM8974GEFL/V Wolfson Microelectronics, WM8974GEFL/V Datasheet - Page 55

Audio CODECs Mono Codec with Spkr

WM8974GEFL/V

Manufacturer Part Number
WM8974GEFL/V
Description
Audio CODECs Mono Codec with Spkr
Manufacturer
Wolfson Microelectronics
Datasheet

Specifications of WM8974GEFL/V

Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
QFN-24
Minimum Operating Temperature
- 25 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Production Data
w
MASTER CLOCK AND PHASE LOCKED LOOP (PLL)
Figure 31 PLL and Clock Select Circuit
Table 51 Sample Rate Control
The PLL can be enabled or disabled by the PLLEN register bit.
Note: In order to minimise current consumption, the PLL is disabled when the VMIDSEL[1:0] bits are
set to 00b. VMIDSEL[1:0] must be set to a value other than 00b to enable the PLL.
Table 52 PLLEN Control Bit
The WM8974 has an on-chip phase-locked loop (PLL) circuit that can be used to:
Generate master clocks for the WM8974 audio functions from another external clock, e.g. in
telecoms applications.
Generate and output (on pin CSB/GPIO) a clock for another part of the system that is derived from
an existing audio master clock.
Figure 31 shows the PLL and internal clocki uxiliary
R7
Additional control
R1
Power management
1
REGISTER
ADDRESS
REGISTER
ADDRESS
3:1
BIT
5
BIT
SR
LABEL
PLLEN
LABEL
000
0
DEFAULT
DEFAULT
ent on the WM8974.
PLL enable
0=PLL off
1=PLL on
Approximate sample rate (configures the
coefficients for the internal digital filters):
000=48kHz
001=32kHz
010=24kHz
011=16kHz
100=12kHz
101=8kHz
110-111=reserved
PD, Rev 4.5, September 2008
DESCRIPTION
DESCRIPTION
WM8974
55

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