Audio CODECs VoIP Mono CODEC

WM8510GEDS/V

Manufacturer Part NumberWM8510GEDS/V
DescriptionAudio CODECs VoIP Mono CODEC
ManufacturerWolfson Microelectronics
WM8510GEDS/V datasheet
 


Specifications of WM8510GEDS/V

Operating Supply Voltage- 0.3 V to + 7 VMaximum Operating Temperature+ 85 C
Mounting StyleSMD/SMTPackage / CaseSSOP-28
Minimum Operating Temperature- 25 CLead Free Status / RoHS StatusLead free / RoHS Compliant
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WM8510
DIGITAL AUDIO INTERFACES
The audio interface has four pins:
The clock signals BCLK, and FRAME can be outputs when the WM8510 operates as a master, or
inputs when it is a slave (see Master and Slave Mode Operation, below).
Five different audio data formats are supported:
All of these modes are MSB first. They are described in Audio Data Formats, below. Refer to the
Electrical Characteristic section for timing information.
MASTER AND SLAVE MODE OPERATION
The WM8510 audio interface may be configured as either master or slave. As a master interface
device the WM8510 generates BCLK and FRAME and thus controls sequencing of the data transfer
on ADCDAT and DACDAT. To set the device to master mode register bit MS should be set high. In
slave mode (MS=0), the WM8510 responds with data to clocks it receives over the digital audio
interfaces.
AUDIO DATA FORMATS
In Left Justified mode, the MSB is available on the first rising edge of BCLK following an FRAME
transition. The other bits up to the LSB are then transmitted in order. Depending on word length,
BCLK frequency and sample rate, there may be unused BCLK cycles before each FRAME transition.
Figure 25 Left Justified Audio Interface (assuming n-bit word length)
In Right Justified mode, the LSB is available on the last rising edge of BCLK before a FRAME
transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK
frequency and sample rate, there may be unused BCLK cycles after each FRAME transition.
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ADCDAT: ADC data output
DACDAT: DAC data input
FRAME: Data alignment clock
BCLK: Bit clock, for synchronisation
Left justified
Right justified
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DSP mode A
Production Data
PD, Rev 4.5 ,September 2008
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