WM8510GEDS/V Wolfson Microelectronics, WM8510GEDS/V Datasheet - Page 55

• Manufacturer Part Number: WM8510GEDS/V
• Description: Audio CODECs VoIP Mono CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8510GEDS/V

• Operating Supply Voltage: - 0.3 V to + 7 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-28
• Minimum Operating Temperature: - 25 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Production Data
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The PLL frequency ratio R = f
EXAMPLE:
MCLK=12MHz, required clock = 12.288MHz.
R should be chosen to ensure 5 < PLLN < 13. There is a fixed divide by 4 in the PLL and a
selectable divide by N after the PLL which should be set to divide by 2 to meet this requirement.
Enabling the divide by 2 sets the required f
Table 47 PLL Frequency Ratio Control
The PLL performs best when f
are shown in Table 48.
Table 48 PLL Frequency Examples
MCLK
(MHz)
19.68
19.68
14.4
14.4
19.2
19.2
19.8
19.8
(F1)
R36
PLL N value
R37
PLL K value 1
R38
PLL K Value 2
R39
PLL K Value 3
12
12
13
13
24
24
26
26
27
27
REGISTER
ADDRESS
PLLN = int R
PLLK = int (2
R = 98.304 / 12 = 8.192
PLLN = int R = 8
k = int ( 2
DESIRED
OUTPUT
11.2896
11.2896
11.2896
11.2896
11.2896
11.2896
11.2896
11.2896
11.2896
12.288
12.288
12.288
12.288
12.288
12.288
12.288
12.288
12.288
(MHz)
4
3:0
5:0
8:0
8:0
24
BIT
x (8.192 – 8)) = 3221225 = 3126E9h
24
90.3168
90.3168
90.3168
90.3168
90.3168
90.3168
90.3168
90.3168
90.3168
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
(MHz)
(R-PLLN))
F2
PLLPRESCALE
PLLN
PLLK [23:18]
PLLK [17:9]
PLLK [8:0]
2
/f
2
1
is around 90MHz. Its stability peaks at N=8. Some example settings
(see Figure 31) can be set using the register bits PLLK and PLLN:
LABEL
PRESCALE
DIVIDE
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
= 4 x 2 x 12.288MHz = 98.304MHz.
0
1000
0Ch
093h
0E9h
DEFAULT
POSTSCALE
DIVIDE
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1= Divide MCLK by 2 before input to
PLL
Integer (N) part of PLL input/output
0 = MCLK input not divided (default)
frequency ratio. Use values greater
than 5 and less than 13.
Fractional (K) part of PLL1
input/output frequency ratio (treat as
one 24-digit binary number).
6.947446
7.561846
6.826667
9.178537
9.990243
9.122909
9.929697
6.947446
7.561846
6.690133
7.281778
7.5264
7.5264
8.192
6.272
9.408
10.24
8.192
PD, Rev 4.5, September 2008
R
DESCRIPTION
(Hex)
A
7
8
6
7
6
6
9
9
9
9
9
7
8
6
7
6
7
N
WM8510
BOAC93
45A1CA
D3A06E
F28BD4
3D70A3
2DB492
FD809F
EE009E
F28BD4
86C226
3126E8
8FD525
6872AF
86C226
3126E8
8FD525
1F76F7
482296
(Hex)
K
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