WM8750BLGEFL/R Wolfson Microelectronics, WM8750BLGEFL/R Datasheet
WM8750BLGEFL/R
Specifications of WM8750BLGEFL/R
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WM8750BLGEFL/R Summary of contents
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... Audio sample rates: 8, 11.025, 16, 22.05, 24, 32, 44.1, 48, 88.2, 96kHz generated internally from master clock • 5x5x0.9mm QFN package APPLICATIONS • Portable Media Player • Mobile phone handsets • Mobile gaming at http://www.wolfsonmicro.com/enews/ WM8750BL Production Data, August 2008, Rev 4.0 Copyright ©2008 Wolfson Microelectronics plc ...
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WM8750BL DESCRIPTION ................................................................................................................. 1 FEATURES ...................................................................................................................... 1 APPLICATIONS ............................................................................................................... 1 BLOCK DIAGRAM ........................................................................................................... 1 TABLE OF CONTENTS ................................................................................................... 2 PIN CONFIGURATION..................................................................................................... 3 ORDERING INFORMATION ............................................................................................ 3 PIN DESCRIPTION .......................................................................................................... 4 ABSOLUTE MAXIMUM RATINGS ................................................................................... 5 RECOMMENDED OPERATION CONDITIONS ................................................................ 5 ...
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... Production Data PIN CONFIGURATION ORDERING INFORMATION ORDER CODE TEMPERATURE RANGE WM8750BLGEFL -25°C to +85°C WM8750BLGEFL/R -25°C to +85°C Note: Reel quantity = 3500 w PACKAGE MOISTURE SENSITIVITY LEVEL 32-lead QFN (5x5x0.9mm) MSL1 (Pb-free) 32-lead QFN (5x5x0.9mm) MSL1 (Pb-free, tape and reel) WM8750BL PEAK SOLDERING ...
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WM8750BL PIN DESCRIPTION PIN NO NAME 1 MCLK Digital Input Supply 2 DCVDD Supply 3 DBVDD 4 DGND Supply 5 BCLK Digital Input / Output 6 DACDAT Digital Input 7 DACLRC Digital Input / Output 8 ADCDAT Digital Output Digital ...
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Production Data ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical ...
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WM8750BL ELECTRICAL CHARACTERISTICS Test Conditions DCVDD = 1.5V, DBVDD = 3.3V, AVDD = HPVDD = 3.3V, T PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER Analogue Inputs (LINPUT1, RINPUT1, LINPUT2, RINPUT2, LINPUT3, RINPUT3) to ADC out Full ...
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Production Data Test Conditions DCVDD = 1.5V, DBVDD = 3.3V, AVDD = HPVDD = 3.3V, T PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER Speaker Output (LOUT2/ROUT2 with 8Ω bridge tied load, ROUT2INV=1) Output Power at 1% ...
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WM8750BL TYPICAL PERFORMANCE POWER CONSUMPTION The power consumption of the WM8750BL depends on the following factors. • Supply voltages: Reducing the supply voltages also reduces supply currents, and therefore results in significant power savings, especially in the digital sections of ...
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Production Data OUTPUT DRIVERS 10 1 0.1 0.01 0 0.1 0.01 1 Notes: 1. These graphs show THD+N relative to the signal amplitude at each point (not relative to full scale). 2. Signal frequency = 1kHz w Headphone ...
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WM8750BL OUTPUT PGA’S LINEARITY 10.000 0.000 Output PGA Gains -10.000 -20.000 -30.000 -40.000 -50.000 -60.000 -70.000 40 50 2.000 1.750 Output PGA Gain Step Size 1.500 1.250 1.000 0.750 0.500 0.250 0.000 XXXVOL ...
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Production Data SIGNAL TIMING REQUIREMENTS SYSTEM CLOCK TIMING MCLK Figure 1 System Clock Timing Requirements Test Conditions CLKDIV2=0, DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, T unless otherwise stated. PARAMETER System Clock Timing Information MCLK System clock pulse ...
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WM8750BL Test Conditions DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, T otherwise stated. PARAMETER Bit Clock Timing Information BCLK rise time (10pF load) BCLK fall time (10pF load) BCLK duty cycle (normal mode, BCLK = MCLK/n) BCLK duty ...
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Production Data CONTROL INTERFACE TIMING – 3-WIRE MODE SCLK SDIN Figure 4 Control Interface Timing – 3-Wire Serial Control Mode Test Conditions DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, T otherwise stated. PARAMETER Program Register Input Information SCLK ...
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WM8750BL CONTROL INTERFACE TIMING – 2-WIRE MODE SDIN SCLK Figure 5 Control Interface Timing – 2-Wire Serial Control Mode Test Conditions DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, T otherwise stated. PARAMETER Program Register Input Information SCLK Frequency ...
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Production Data INTERNAL POWER ON RESET CIRCUIT AVDD Figure 6 Internal Power on Reset Circuit Schematic The WM8750BL includes an internal Power-On-Reset Circuit, as shown in Figure 6, which is used to reset the digital logic into a default state ...
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WM8750BL DEVICE DESCRIPTION INTRODUCTION The WM8750BL is a low power audio codec offering a combination of high quality audio, advanced features, low power and small size. These characteristics make it ideal for portable digital audio applications such as MP3 and ...
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Production Data The signal inputs are biased internally to the reference voltage VREF. Whenever the line inputs are muted or the device placed into standby mode, the inputs are kept biased to VREF using special anti-thump circuitry. This reduces any ...
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WM8750BL MONO MIXING The stereo ADC can operate as a stereo or mono device, or the two channels can be mixed to mono in the analogue domain (i.e. before the ADC). MONOMIX selects the mode of operation; either the left ...
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Production Data PGA CONTROL The PGA matches the input signal level to the ADC input range. The PGA gain is logarithmically adjustable from +30dB to –17.25dB in 0.75dB steps. Each PGA can be controlled either by the user or by ...
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WM8750BL ANALOGUE TO DIGITAL CONVERTER (ADC) The WM8750BL uses a multi-bit, oversampled sigma-delta ADC for each channel. The use of multi- bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. The ADC Full Scale ...
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Production Data REGISTER R5 (05h) ADC and DAC Control R27 (1Bh) Table 10 ADC Signal Path Control Table 11 ADC High Pass Filter Enable Modes w BIT LABEL ADDRESS 6:5 ADCPOL [1:0] 4 HPOR 0 ADCHPD 5 HPFLREN HPFLREN ADCHPD ...
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WM8750BL DIGITAL ADC VOLUME CONTROL The output of the ADCs can be digitally amplified or attenuated over a range from –97dB to +30dB in 0.5dB steps. The volume of each channel can be controlled separately. The gain for a given ...
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Production Data AUTOMATIC LEVEL CONTROL (ALC) The WM8750BL has an automatic level control that aims to keep a constant recording volume irrespective of the input signal level. This is achieved by continuously adjusting the PGA gain so that the signal ...
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WM8750BL REGISTER ADDRESS R17 (11h) ALC Control 1 R18 (12h) ALC Control 2 R19 (13h) ALC Control 3 Table 13 ALC Control Note: For correct ALC operation in differential input mode it is recommended that the ALC is not used ...
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Production Data PEAK LIMITER To prevent clipping when a large signal occurs just after a period of quiet, the ALC circuit includes a limiter function. If the ADC input signal exceeds 87.5% of full scale (–1.16dB), the PGA gain is ...
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WM8750BL 3D STEREO ENHANCEMENT The WM8750BL has a digital 3D enhancement option to artificially increase the separation between the left and right channels. This effect can be used for recording or playback, but not for both simultaneously. Selection of 3D ...
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Production Data OUTPUT SIGNAL PATH The WM8750BL output signal paths consist of digital filters, DACs, analogue mixers and output drivers. The digital filters and DACs are enabled when the WM8750BL is in ‘playback only’ or ‘record and playback’ mode. The ...
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WM8750BL GRAPHIC EQUALISER The WM8750BL has a digital graphic equaliser and adaptive bass boost function. This function operates on digital audio data before it is passed to the audio DACs. Bass enhancement can take two different forms: • Linear bass ...
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Production Data DIGITAL TO ANALOGUE CONVERTER (DAC) After passing through the graphic equaliser filters, digital ‘de-emphasis’ can be applied to the audio data if necessary (e.g. when the data comes from a CD with pre-emphasis used in the recording). De-emphasis ...
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WM8750BL OUTPUT MIXERS The WM8750BL provides the option to mix the DAC output signal with analogue line-in signals from the LINPUT1/2/3, RINPUT1/2/3 pins or a mono differential input (LINPUT1 – RINPUT1) or (LINPUT2 – RINPUT2), selected by DS (see Table ...
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Production Data REGISTER ADDRESS R36 (24h) Right Mixer Control (1) R37 (25h) Right Mixer Control (2) Table 23 Right Output Mixer Control REGISTER ADDRESS R38 (26h) Mono Mixer Control (1) R39 (27h) Mono Mixer Control (2) Table 24 Mono Output ...
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WM8750BL ANALOGUE OUTPUTS LOUT1/ROUT1 OUTPUTS The LOUT1 and ROUT1 pins can drive a 16Ω or 32Ω headphone or a line output (see Headphone Output and Line Output sections, respectively). The signal volume on LOUT1 and ROUT1 can be independently adjusted ...
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Production Data LOUT2/ROUT2 OUTPUTS The LOUT2 and ROUT2 output pins are essentially similar to LOUT1 and ROUT1, but they are independently controlled and can also drive an 8Ω mono speaker (see Speaker Output section). For speaker drive, the ROUT2 signal ...
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WM8750BL ENABLING THE OUTPUTS Each analogue output of the WM8750BL can be separately enabled or disabled. The analogue mixer associated with each output is powered on or off along with the output pin. All outputs are disabled by default. To ...
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Production Data REGISTER ADDRESS R24 (18h) Additional Control (2) Table 32 Headphone Switch Figure 11 Example Headset Detection Circuit Using Normally-Open Switch Figure 12 Example Headset Detection Circuit Using Normally-Closed Switch THERMAL SHUTDOWN The speaker and headphone outputs can drive ...
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WM8750BL HEADPHONE OUTPUT Analogue outputs LOUT1/ROUT1, LOUT2/ROUT2, and OUT3, can drive a 16Ω or 32Ω headphone load, either through DC blocking capacitors coupled without any capacitor. Headphone Output using DC blocking Figure 13 Recommended Headphone Output Configurations When ...
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Production Data LINE OUTPUT The analogue outputs, LOUT1/ROUT1 and LOUT2/ROUT2, can be used as line outputs. Additionally, OUT3 and MONOOUT can be used as a stereo line-out by setting OUT3SW=11 (reg. 24) and ensuring the contents of registers 38 and ...
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WM8750BL Note: For optimum ADC audio performance in slave mode, the BCLK input signal should be configured to transition at the same time as the falling edge of MCLK. The ADCDAT digital data output is buffered inside the CODEC using ...
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Production Data In DSP/PCM mode, the left channel MSB is available on either the 1 rising edge of BCLK (selectable by LRP) following a rising edge of LRC. Right channel data immediately follows left channel data. Depending on word length, ...
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WM8750BL Figure 22 DSP/PCM Mode Audio Interface (mode A, LRP=0, Slave) Figure 23 DSP/PCM Mode Audio Interface (mode B, LRP=0, Slave) w Production Data PD, Rev 4.0, August 2008 40 ...
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Production Data AUDIO INTERFACE CONTROL The register bits controlling audio format, word length and master / slave mode are summarised in Table 34. MS selects audio interface operation in master or slave mode. In Master mode BCLK, ADCLRC and DACLRC ...
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WM8750BL MASTER MODE ADCLRC AND DACLRC ENABLE In Master mode, by default ADCLRC is disabled when the ADC is disabled and DACLRC is disabled when the DAC is disabled. Register bit LRCM, register 24(18h) bit[2] changes the control so that ...
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Production Data CLOCK OUTPUT By default ADCLRC (pin 9) is the ADC word clock input/output. Under the control of ADCLRM[1:0], register 27(1Bh) bits [8:7] the ADCLRC pin may be configured as a clock output. If ADCLRM is 01 ...
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WM8750BL MCLK MCLK ADC SAMPLE RATE CLKDIV2=0 CLKDIV2=1 ‘Normal’ Clock Mode (‘*’ indicates backward compatibility with WM8731) 8 kHz (MCLK/1536) 12.288 MHz 24.576 MHz 8 kHz (MCLK/1536) 12 kHz (MCLK/1024) 16 kHz (MCLK/768) 24 kHz (MCLK/512) 32 kHz (MCLK/384) 48 ...
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Production Data CONTROL INTERFACE SELECTION OF CONTROL MODE The WM8750BL is controlled by writing to registers through a serial control interface. A control word consists of 16 bits. The first 7 bits (B15 to B9) are address bits that select ...
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WM8750BL The WM8750BL has two possible device addresses, which can be selected using the CSB pin. CSB STATE Table 42 2-Wire MPU Interface Address Selection POWER SUPPLIES The WM8750BL can use up to four separate power supplies: • AVDD / ...
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Production Data REGISTER ADDRESS R25 (19h) Power Management (1) R26 (1Ah) Power Management (2) * The left mixer is enabled when LOUT1=1 or LOUT2=1. The right mixer is enabled when ROUT1=1 or ROUT2=1. Table 43 Power Management w BIT LABEL ...
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WM8750BL STOPPING THE MASTER CLOCK In order to minimise power consumed in the digital core of the WM8750BL, the master clock may be stopped in Standby and OFF modes. If this cannot be done externally at the clock source, the ...
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Production Data REGISTER MAP ADDRESS REGISTER remarks (Bit 15 – (00h) 0000000 Left Input volume R1 (01h) 0000001 Right Input volume R2 (02h) 0000010 LOUT1 volume R3 (03h) 0000011 ROUT1 volume R4 (04h) 0000100 Reserved R5 (05h) 0000101 ...
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WM8750BL DIGITAL FILTER CHARACTERISTICS The ADC and DAC employ different digital filters. There are 4 types of digital filter, called Type and 3. The performance of Types 0 and 1 is listed in the table below, the ...
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Production Data DAC FILTER RESPONSES 0 -20 -40 -60 -80 -100 0 0.5 1 1.5 Frequency (Fs) Figure 27 DAC Digital Filter Frequency Response – Type 0 Figure 28 DAC Digital Filter Ripple – Type 0 0 -20 -40 -60 ...
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WM8750BL 0 -20 -40 -60 -80 -100 0 0.5 1 1.5 Frequency (Fs) Figure 33 DAC Digital Filter Frequency Response – Type 3 Figure 34 DAC Digital Filter Ripple – Type 3 ADC FILTER RESPONSES 0 -20 -40 -60 -80 ...
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Production Data 0 -20 -40 -60 -80 -100 0 0.5 1 1.5 Frequency (Fs) Figure 39 ADC Digital Filter Frequency Response – Type 2 0 -20 -40 -60 -80 -100 0 0.5 1 1.5 Frequency (Fs) Figure 41 ADC Digital ...
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WM8750BL -10 0 5000 10000 Frequency (Fs) Figure 45 De-emphasis Frequency Response (44.1kHz -10 0 5000 10000 Frequency (Fs) Figure 47 De-emphasis Frequency Response (48kHz) HIGHPASS FILTER The WM8750BL has ...
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Production Data APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS Figure 50 Recommended External Components Diagram w WM8750BL PD, Rev 4.0, August 2008 55 ...
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WM8750BL LINE INPUT CONFIGURATION When LINPUT1/RINPUT1 or LINPUT2/RINPUT2 are used as line inputs, the microphone boost and ALC functions should normally be disabled. In order to avoid clipping, the user must ensure that the input signal does not exceed AVDD. ...
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Production Data POWER MANAGEMENT EXAMPLES OPERATION MODE Stereo Headphone Playback Stereo Line-in Record Stereo Microphone Record Mono Microphone Record Stereo Line-in to Headphone Out Phone Call Speaker Phone Call [ROUT2INV = 1] Record Phone Call [L channel = mic with ...
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WM8750BL PACKAGE DIMENSIONS FL: 32 PIN QFN PLASTIC PACKAGE 5 CORNER D2 TIE BAR B D2 EXPOSED 6 GROUND PADDLE BOTTOM VIEW (A3) 1 SIDE VIEW C SEATING PLANE DETAIL B ...
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... Production Data IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice ...