WM8983GEFL/V Wolfson Microelectronics, WM8983GEFL/V Datasheet
WM8983GEFL/V
Specifications of WM8983GEFL/V
Related parts for WM8983GEFL/V
WM8983GEFL/V Summary of contents
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... QFN package APPLICATIONS • Multimedia mobile phones at http://www.wolfsonmicro.com/enews WM8983 Production Data, May 2010, Rev 4.3 Copyright ©2010 Wolfson Microelectronics plc ...
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WM8983 BLOCK DIAGRAM w Production Data PD, Rev 4.3, May 2010 2 ...
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Production Data DESCRIPTION ....................................................................................................... 1 FEATURES ............................................................................................................ 1 APPLICATIONS ..................................................................................................... 1 BLOCK DIAGRAM ................................................................................................. 2 TABLE OF CONTENTS ......................................................................................... 3 PIN CONFIGURATION ........................................................................................... 5 ORDERING INFORMATION .................................................................................. 5 PIN DESCRIPTION ................................................................................................ 6 ABSOLUTE MAXIMUM RATINGS......................................................................... 7 RECOMMENDED OPERATING CONDITIONS ..................................................... ...
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WM8983 HIGHPASS FILTER ................................................................................................... 117 5-BAND EQUALISER ................................................................................................ 118 APPLICATIONS INFORMATION ....................................................................... 122 RECOMMENDED EXTERNAL COMPONENTS ........................................................ 122 IMPORTANT NOTICE ........................................................................................ 124 ADDRESS: ................................................................................................................ 124 w Production Data PD, Rev 4.3, May 2010 4 ...
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... Production Data PIN CONFIGURATION ORDERING INFORMATION TEMPERATURE ORDER CODE RANGE WM8983GEFL/V -25°C to +85°C WM8983GEFL/RV -25°C to +85°C Note: Reel quantity = 3,500 w MOISTURE PACKAGE SENSITIVITY LEVEL 32-lead QFN ( mm) (pb-free) 32-lead QFN ( mm) (pb-free, tape and reel) WM8983 PEAK SOLDERING TEMPERATURE o MSL3 260 ...
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WM8983 PIN DESCRIPTION PIN NAME 1 LIP Analogue input 2 LIN Analogue input 3 L2/GPIO2 Analogue input Analogue input 4 RIP 5 RIN Analogue input 6 R2/GPIO3 Analogue input 7 LRC Digital Input / Output 8 BCLK Digital Input / ...
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Production Data ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical ...
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WM8983 ELECTRICAL CHARACTERISTICS Test Conditions DCVDD=1.8V, AVDD1=AVDD2=DBVDD=3.3V, T PARAMETER Microphone Input PGA Inputs (LIP, LIN, RIP, RIN, L2, R2) INPPGAVOLL, INPPGAVOLR, PGABOOSTL and PGABOOSTR = 0dB Full-scale Input Signal Level – 1 Single-ended input via LIN/RIN Full-scale Input Signal Level ...
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Production Data Test Conditions DCVDD=1.8V, AVDD1=AVDD2=DBVDD=3.3V, T PARAMETER Auxiliary Analogue Inputs (AUXL, AUXR) 2 Full-scale Input Signal Level Input Resistance Input Capacitance Gain range from AUXL and AUXR input to left and right input PGA mixers AUXLBOOSTVOL and AUXRBOOSTVOL step ...
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WM8983 Test Conditions DCVDD=1.8V, AVDD1=AVDD2=DBVDD=3.3V, T PARAMETER Analogue to Digital Converter (ADC) - Input from L2, R2 into right PGA mixer. L2_2INPPGA and R2_2INPPGA = 0. INPPGAVOLL, INPPGAVOLR, L2_2BOOSTVOL, R2_2BOOSTVOL, ADCLVOL and ADCRVOL = 0dB 3 Signal to Noise Ratio ...
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Production Data Test Conditions DCVDD=1.8V, AVDD1=AVDD2=DBVDD=3.3V, T PARAMETER 4 Total Harmonic Distortion 5 Total Harmonic Distortion + Noise 6 Channel Separation DAC to left and right mixer into headphone (16Ω load) on LOUT2 and ROUT2 LOUT2VOL, ROUT2VOL, DACLVOL and DACRVOL ...
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WM8983 Test Conditions DCVDD=1.8V, AVDD1=AVDD2=DBVDD=3.3V, T PARAMETER 6 Channel Separation LIN and RIN into input PGA Bypass to LOUT1 and ROUT1 into 10kΩ / 50pF loads BYPLMIXVOL, BYPRMIXVOL, LOUT1VOL and ROUT1VOL = 0dB Full-scale output voltage, 0dB gain 3 SIGNAL ...
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Production Data Test Conditions DCVDD=1.8V, AVDD1=AVDD2=DBVDD=3.3V, T PARAMETER Digital Input / Output Input HIGH Level Input LOW Level Output HIGH Level Output LOW Level Input Capacitance TERMINOLOGY 1. Full-scale input and output levels scale in relation to AVDD or AVDD2 ...
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WM8983 SPEAKER OUTPUT THD VERSUS POWER utp ...
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Production Data Audio Precision W M8983 THD+N vs. Output Power -- Boost enabled; SPKVDD=4. -20 -30 d -40 B -50 r -60 A -70 -80 -90 -100 0 100m 200m Sweep Trace Color ...
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WM8983 POWER CONSUMPTION TYPICAL SCENARIOS Estimated current consumption for typical scenarios are shown below. Power delivered to the load is not included. MODE Off (No clocks, temperature sensor disabled) Sleep (VREF maintained) Mono Record from Differential MIC (8kHz, PLL enabled) ...
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Production Data AUDIO PATHS OVERVIEW w WM8983 PD, Rev 4.3, May 2010 17 ...
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WM8983 SIGNAL TIMING REQUIREMENTS SYSTEM CLOCK TIMING MCLK Figure 5 System Clock Timing Requirements Test Conditions DCVDD=1.8V, DBVDD=AVDD1=AVDD2=3.3V, DGND=AGND1=AGND2=0V, T PARAMETER System Clock Timing Information MCLK cycle time MCLK duty cycle Note: 1. PLL pre-scaling and PLL N and K ...
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Production Data Test Conditions DCVDD=1.8V, DBVDD=AVDD1=AVDD2=3.3V, DGND=AGND1=AGND2=0V, T 24-bit data, unless otherwise stated. PARAMETER Audio Data Input Timing Information LRC propagation delay from BCLK falling edge ADCDAT propagation delay from BCLK falling edge DACDAT setup time to BCLK rising edge ...
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WM8983 CONTROL INTERFACE TIMING – 3-WIRE MODE 3-wire mode is selected by connecting the MODE pin high. Figure 8 Control Interface Timing – 3-Wire Serial Control Mode Test Conditions DCVDD=1.8V, DBVDD=AVDD1=AVDD2=3.3V, DGND=AGND1=AGND2=0V, T 24-bit data, unless otherwise stated. PARAMETER Program ...
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Production Data CONTROL INTERFACE TIMING – 2-WIRE MODE 2-wire mode is selected by connecting the MODE pin low. SDIN SCLK Figure 9 Control Interface Timing – 2-Wire Serial Control Mode Test Conditions DCVDD=1.8V, DBVDD=AVDD1=AVDD2=3.3V, MCLK=256fs, 24-bit data, unless otherwise stated. ...
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WM8983 INTERNAL POWER ON RESET CIRCUIT Figure 10 Internal Power on Reset Circuit Schematic The WM8983 includes an internal Power-On-Reset Circuit, as shown in Figure 10, which is used reset the digital logic into a default state after power up. ...
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Production Data Figure 12 Typical Power up Sequence where DCVDD is Powered before AVDD1 Figure 12 shows a typical power-up sequence where DCVDD comes up first. First it is assumed that DCVDD is already up to specified operating voltage. When ...
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WM8983 RECOMMENDED POWER UP/DOWN SEQUENCE In order to minimise output pop and click noise recommended that the WM8983 device is powered up and down under control using the following sequences: Power Up: • Turn on external power supplies. ...
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Production Data Figure 13 ADC Power Up and Down Sequence (not to scale) SYMBOL t midrail_on t midrail_off t adcint ADC Group Delay Table 3 Typical POR Operation (typical simulated values) w MIN TYPICAL MAX UNIT 300 ms >6 s ...
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WM8983 Notes: 1. The analogue input pin charge time, t time is dependent upon the value of VMID decoupling capacitor and VMID pin input resistance and AVDD power supply rise time. 2. The analogue input pin discharge time, t capacitor ...
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Production Data Notes: 1. The lineout charge time, t dependent upon the value of VMID decoupling capacitor and VMID pin input resistance and AVDD power supply rise time. The values above were measured using a 4.7μF capacitor ...
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WM8983 DEVICE DESCRIPTION INTRODUCTION The WM8983 is a low power audio CODEC combining a high quality stereo audio DAC and ADC, with flexible line and microphone input and output processing. FEATURES The chip offers great flexibility in use, and so ...
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Production Data OUT3 and OUT4 can be configured to provide an additional stereo or mono differential lineout from the output of the DACs, the mixers or the input microphone boost stages. They can also provide a midrail reference for pseudo ...
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WM8983 INPUT SIGNAL PATH The WM8983 has a number of flexible analogue inputs. There are two input channels, Left and Right, each of which consists of an input PGA stage followed by a boost/mix stage which drives into the hi-fi ...
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Production Data The input PGAs are enabled by the INPPGAENL and INPPGAENR register bits. REGISTER ADDRESS R2 Power Management 2 Table 5 Input PGA Enable Register Settings REGISTER ADDRESS R44 Input Control Table 6 Input PGA Control INPUT PGA VOLUME ...
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WM8983 REGISTER ADDRESS R45 Left channel input PGA volume control R46 Right channel input PGA volume control R32 ALC control 1 Table 7 Input PGA Volume Control w BIT LABEL DEFAULT 5:0 INPPGAVOLL 010000 6 INPPGAMUTEL 0 7 INPPGAZCL 0 ...
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Production Data VOLUME UPDATES Volume settings will not be applied to the PGAs until a ‘1’ is written to one of the INPPGAVU bits. This is to allow left and right channels to be updated at the same time, as ...
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WM8983 Figure 18 Volume Update Using Zero Cross Detection If there is a long period where no zero-crossing occurs, a timeout circuit in the WM8983 will automatically update the volume. The volume updates will occur between one and two timeout ...
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Production Data AUXILLIARY INPUTS There are two auxiliary inputs, AUXL and AUXR which can be used for a variety of purposes such as stereo line inputs ‘beep’ input signal to be mixed with the outputs. As signal ...
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WM8983 The input PGA paths can have a +20dB boost (PGABOOSTL/R= 0dB pass through (PGABOOSTL/R= completely isolated from the input boost circuit (INPPGAMUTEL/R=1). REGISTER ADDRESS R47 Left Input BOOST control R48 Right Input BOOST control Table ...
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Production Data REGISTER ADDRESS R42 OUT4 to ADC R47 Left channel Input BOOST control R48 Right channel Input BOOST control w BIT LABEL DEFAULT 8:6 OUT4_2ADCVOL 000 5 OUT4_2LNR 0 2:0 AUXL2BOOSTVOL 000 6:4 L2_2BOOSTVOL 000 2:0 AUXR2BOOSTVOL 000 WM8983 ...
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WM8983 REGISTER ADDRESS Table 9 Input BOOST Stage Control The BOOST stage is enabled under control of the BOOSTEN register bit. REGISTER ADDRESS R2 Power management 2 Table 10 Input BOOST Enable Control MICROPHONE BIASING CIRCUIT The MICBIAS output provides ...
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Production Data VMI Figure 21 Microphone Bias Schematic ANALOGUE TO DIGITAL CONVERTER (ADC) The WM8983 uses stereo multi-bit, oversampled sigma-delta ADCs. The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. The ...
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WM8983 The polarity of the output signal can also be changed under software control using the ADCLPOL/ADCRPOL register bit. ADCOSR register bit. With ADCOSR=0 the oversample rate is 64x which gives lowest power operation and when ADCOSR=1 the oversample rate ...
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Production Data PROGRAMMABLE IIR NOTCH FILTER A programmable notch filter is provided. This filter has a variable centre frequency and bandwidth, programmable via two coefficients, a NFA0[13:0] and NFA1[13:0]. Because these coefficient values require four register writes to setup there ...
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WM8983 NOTCH FILTER WORKED EXAMPLE The following example illustrates how to calculate the a frequency and -3dB bandwidth 1000 100 48000 ...
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Production Data DIGITAL ADC VOLUME CONTROL The output of the ADCs can be digitally attenuated over a range from –127dB to 0dB in 0.5dB steps. The gain for a given eight-bit code X is given by: 0.5 × (G-255) dB ...
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WM8983 INPUT LIMITER / AUTOMATIC LEVEL CONTROL (ALC) The WM8983 has an automatic PGA gain control circuit, which can function as an input peak limiter automatic level control (ALC). The Automatic Level Control (ALC) provides continuous adjustment ...
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Production Data REGISTER ADDRESS R34 (22h) ALC Control 3 w BIT LABEL DEFAULT 7:4 ALCHLD 0000 [3:0] (0ms) 8 ALCMODE 0 7:4 ALCDCY 0011 [3:0] (13ms/6dB) 0011 (2.9ms/6dB) 3:0 ALCATK 0010 [3:0] (832us/6dB) WM8983 DESCRIPTION ALC hold time before gain ...
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WM8983 REGISTER ADDRESS Table 19 ALC Control Registers When the ALC is disabled, the input PGA remains at the last controlled value of the ALC. An input gain update must be made by writing to the INPPGAVOLL/R register bits. NORMAL ...
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Production Data LIMITER MODE In limiter mode, the ALC will reduce peaks that go above the threshold level, but will not increase the PGA gain beyond the starting level. The starting level is the PGA gain setting when the ALC ...
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WM8983 Note: R32, R33, R45 and R46 register settings above need to be changed to reflect settings required in the target application. ATTACK AND DECAY TIMES The attack and decay times set the update times for the PGA gain. The ...
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Production Data LIMITER MODE ALCMODE = 1 (Limiter Mode) ALCATK 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 ALCMODE = 1 (Limiter Mode) ALCDCY 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 Table 21 ...
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WM8983 MINIMUM AND MAXIMUM GAIN The ALCMIN and ALCMAX register bits set the minimum/maximum gain value that the PGA can be set to whilst under the control of the ALC. This has no effect on the PGA when ALC is ...
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Production Data ALCMIN 000 001 010 011 100 101 110 111 Table 24 ALC Min Gain Values Note that if the ALC gain setting strays outside the ALC operating range, either by starting the ALC outside of the range or ...
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WM8983 Figure 26 ALCLVL w Production Data PD, Rev 4.3, May 2010 52 ...
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Production Data Figure 27 ALC Hold Time ALCHLD 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 Table 26 ALC Hold Time Values w t (s) HOLD 0 2.67ms 5.34ms 10.7ms 21.4ms 42.7ms 85.4ms 171ms 342ms 684ms 1.37s ...
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WM8983 PEAK LIMITER To prevent clipping when a large signal occurs just after a period of quiet, the ALC circuit includes a limiter function. If the ADC input signal exceeds 87.5% of full scale (–1.16dB), the PGA gain is ramped ...
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Production Data The diagrams below show the response of the system to the same signal with and without noise gate. Figure 28 ALC Operation Above Noise Gate Threshold w WM8983 PD, Rev 4.3, May 2010 55 ...
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WM8983 Figure 29 Noise Gate Operation OUTPUT SIGNAL PATH The WM8983 output signal paths consist of digital application filters, up-sampling filters, stereo Hi-Fi DACs, analogue mixers, stereo headphone and stereo line/mono/midrail output drivers. The digital filters and DAC are enabled ...
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Production Data The analogue outputs from the DACs can then be mixed with the aux analogue inputs and the ADC analogue inputs. The mix is fed to the output drivers for headphone (LOUT1/ROUT1, LOUT2/ROUT2) or line (OUT3/OUT4). OUT3 and OUT4 ...
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WM8983 DIGITAL HI-FI DAC VOLUME (GAIN) CONTROL The signal volume from each Hi-Fi DAC can be controlled digitally. The gain range is –127dB to 0dB in 0.5dB steps. The level of attenuation for an eight-bit code X is given by: ...
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Production Data Figure 31 DAC Digital Limiter Operation The limiter has a programmable upper threshold which is close to 0dB. Referring to Figure 31, in normal operation (LIMBOOST=000 => limit only) signals below this threshold are unaffected by the limiter. ...
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WM8983 REGISTER ADDRESS R24 DAC digital limiter control 1 R25 DAC digital limiter control 2 Table 31 DAC Digital Limiter Control w BIT LABEL DEFAULT 3:0 LIMATK 0010 7:4 LIMDCY 0011 8 LIMEN 0 3:0 LIMBOOST 0000 6:4 LIMLVL 000 ...
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Production Data 5-BAND GRAPHIC EQUALISER A 5-band graphic equaliser is provided, which can be applied to the ADC or DAC path, together with 3D enhancement, under control of the EQ3DMODE register bit. REGISTER ADDRESS R18 EQ Control 1 Table 32 ...
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WM8983 REGISTER ADDRESS R21 EQ Band 4 Control Table 36 EQ Band 4 Control REGISTER ADDRESS R22 EQ Band 5 Gain Control Table 37 EQ Band 5 Control GAIN REGISTER 11001 to 11111 Table 38 Gain Register Table See also ...
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Production Data 3D STEREO ENHANCEMENT The WM8983 has a digital 3D enhancement option to increase the perceived separation between the left and right channels. Selection of 3D for record or playback is controlled by register bit EQ3DMODE. Switching this bit ...
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WM8983 LEFT AND RIGHT OUTPUT CHANNEL MIXERS The left and right output channel mixers are shown in Figure 32. These mixers allow the AUX inputs, the ADC bypass and the DAC left and right channels to be combined as desired. ...
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Production Data REGISTER ADDRESS R43 Output mixer control R43 Output mixer control R49 Output mixer control R50 Left channel output mixer control w BIT LABEL DEFAULT 8 BYPL2RMIX 0 7 BYPR2LMIX 0 5 DACR2LMIX 0 6 DACL2RMIX 0 0 DACL2LMIX ...
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WM8983 REGISTER ADDRESS R51 Right channel output mixer control R3 Power management 3 Table 40 Left and Right Output Mixer Control w BIT LABEL DEFAULT 0 DACR2RMIX 1 1 BYPR2RMIX 0 4:2 BYPRMIXVOL 000 5 AUXR2RMIX 0 8:6 AUXRMIXVOL 000 ...
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Production Data HEADPHONE OUTPUTS (LOUT1 AND ROUT1) The headphone outputs LOUT1 and ROUT1 can drive a 16Ω or 32Ω headphone load, either through DC blocking capacitors, or DC-coupled to a buffered midrail reference as shown in Figure 33. OUT3, OUT4, ...
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WM8983 REGISTER ADDRESS R52 LOUT1 Volume control R53 ROUT1 Volume control Table 41 OUT1 Volume Control SPEAKER OUTPUTS (LOUT2 AND ROUT2) The outputs LOUT2 and ROUT2 are designed to drive an 8Ω BTL speaker but can optionally drive two headphone ...
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Production Data Figure 34 Speaker Outputs LOUT2 and ROUT2 w WM8983 PD, Rev 4.3, May 2010 69 ...
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WM8983 SPEAKER BOOST MODE To support speaker boost mode, AVDD2 should be at least 1.5*AVDD1. A higher AVDD2 will improve THD performance at the expense of power consumption while lower AVDD2 will cause clipping. Variations in AVDD1 and AVDD2 should ...
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Production Data REGISTER ADDRESS R54 LOUT2 Volume control R55 ROUT2 Volume control Table 42 OUT2 Volume Control The signal output on LOUT2/ROUT2 comes from the Left/Right Mixer circuits and can be any combination of the DAC output, the Bypass path ...
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WM8983 REGISTER ADDRESS R49 Output control R1 Power management 1 Table 43 Speaker Boost Stage Control SPKBOOST Table 44 Output Boost Stage Details REGISTER ADDRESS R43 Beep control Table 45 AUXR – ROUT2 BEEP Mixer Function ZERO CROSS TIMEOUT A ...
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Production Data OUT3/OUT4 MIXERS AND OUTPUT STAGES The OUT3/OUT4 pins provide an additional stereo line output, a mono output pseudo ground connection for headphones. There is a dedicated analogue mixer for OUT3 and one for OUT4 as shown ...
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WM8983 REGISTER ADDRESS R56 OUT3 mixer control R57 OUT4 mixer control Table 47 OUT3/OUT4 Mixer Registers The OUT3 and OUT4 output stages each have a selectable gain boost of 1.5x (3.52dB). When this boost is enabled the output DC level ...
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Production Data Figure 39 Outputs OUT3 and OUT4 REGISTER ADDRESS R49 Output control R1 Power management 1 Table 48 OUT3 and OUT4 Boost Stages Control OUT3BOOST/ OUT4BOOST Table 49 OUT3 and OUT4 Output Boost Stage Details w BIT LABEL 3 ...
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WM8983 OUTPUT PHASING The relative phases of the analogue outputs will depend upon the following factors: 1. DACLPOL and DACRPOL invert bits: Setting these bits to 1 will invert the DAC output. 2. Mixer configuration: The polarity of the signal ...
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Production Data Table 50 shows the polarities of the outputs in various configurations. Unless otherwise stated, polarity is shown with respect to left DAC output in non-inverting mode. Note that only registers relating to the mixer paths are shown here ...
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WM8983 ENABLING THE OUTPUTS Each analogue output of the WM8983 can be independently enabled or disabled. The analogue mixer associated with each output has a separate enable bit. All outputs are disabled by default. To save power, unused parts of ...
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Production Data UNUSED ANALOGUE INPUTS/OUTPUTS Whenever an analogue input/output is disabled, it remains connected to a voltage source (either AVDD1/2 or 1.5xAVDD1/2 as appropriate) through a resistor. This helps to prevent pop noise when the output is re-enabled. The resistance ...
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WM8983 L/ROUT2EN/ OUT3/4EN Table 54 Unused Output Pin Bias Options DIGITAL AUDIO INTERFACES The audio interface has four pins: • • • • The clock signals BCLK, and LRC can be outputs when the WM8983 operates as a master, or ...
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Production Data In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRC transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK frequency and sample rate, there may ...
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WM8983 Figure 45 DSP/PCM Mode Audio Interface (mode A, LRP=0, Master) Figure 46 DSP/PCM Mode Audio Interface (mode B, LRP=1, Master) Figure 47 DSP/PCM Mode Audio Interface (mode A, LRP=0, Slave) w Production Data PD, Rev 4.3, May 2010 82 ...
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Production Data Figure 48 DSP/PCM Mode Audio Interface (mode B, LRP=0, Slave) w WM8983 PD, Rev 4.3, May 2010 83 ...
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WM8983 REGISTER ADDRESS R4 Audio Interface Control R5 Table 55 Audio Interface Control Note: Right Justified Mode will only operate with a maximum of 24 bits. If 32-bit mode is selected the device will operate in 24-bit mode. AUDIO INTERFACE ...
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Production Data REGISTER ADDRESS R6 Clock Generation Control Table 56 Clock Control The CKLSEL bit selects the internal source of the Master clock from the PLL (CLKSEL=1) or from MCLK (CLKSEL=0). When the internal clock is switched from one source ...
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WM8983 AUDIO SAMPLE RATES The WM8983 filter characteristics for the ADCs and the DACs are set using the SR register bits; these bits do not change the rate of the audio interface output clocks in Master mode. The cut-offs for ...
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Production Data Figure 49 PLL and Clock Select Circuit The PLL frequency ratio should be chosen to ensure 5 < PLLN < 13: To calculate R: There is a fixed divide the PLL, ...
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WM8983 REGISTER ADDRESS R36 PLL N value R37 PLL K value 1 R38 PLL K Value 2 R39 PLL K Value 3 Table 59 PLL Frequency Ratio Control The PLL performs best when f are shown in Table 60. MCLK ...
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Production Data COMPANDING The WM8983 supports A-law and μ-law companding on both transmit (ADC) and receive (DAC) sides. Companding can be enabled on the DAC or ADC audio interfaces by writing the appropriate value to the DAC_COMP or ADC_COMP register ...
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WM8983 120 100 Figure 50 μ-Law Companding 120 100 Figure 51 A-Law Companding w u-law Companding 0.1 0.2 0.3 0.4 Normalised Input A-law Companding 0 0 0.2 0.4 Normalised Input ...
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Production Data GENERAL PURPOSE INPUT/OUTPUT The WM8983 has three dual purpose input/output pins. • • • The GPIO2 and GPIO3 functions are provided for use as jack detection inputs. The GPIO1 and GPIO2 functions are provided for use as jack ...
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WM8983 Switching on/off of the outputs is fully configurable by the user. Each output, OUT1, OUT2, OUT3 and OUT4 has 2 associated enables. OUT1_EN_0, OUT2_EN_0, OUT3_EN_0 and OUT4_EN_0 are the output enable signals which are used if the selected jack ...
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Production Data CONTROL INTERFACE SELECTION OF CONTROL MODE AND 2-WIRE MODE ADDRESS The control interface can operate as either a 3-wire or 2-wire control interface. The MODE pin determines the wire mode as shown in Table 65. ...
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WM8983 RESETTING THE CHIP The WM8983 can be reset by performing a write of any value to the software reset register (address 0h). This will cause all register values to be reset to their default values. In addition to this ...
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Production Data BIASEN The analogue amplifiers will not operate unless BIASEN is enabled. REGISTER ADDRESS R1 Power management 1 Table 68 Analogue Bias Control BIAS CONTROL Control of the analog bias values is possible using register 61 and 62 REGISTER ...
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WM8983 REGISTER MAP REGISTER B8 ADDR NAME B[15: Software Reset 1 01 Power manage’t BUFDC 1 OPEN 02 2 Power manage’t ROUT1 Power manage’t OUT4EN ...
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Production Data REGISTER B8 ADDR NAME B[15: Noise Gate PLL PLL PLL PLL ...
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WM8983 REGISTER BITS BY ADDRESS Notes: 1. Default values of N/A indicate non-latched data bits (e.g. software reset or volume update bits). 2. Register bits marked “s "Reser”ed" should not be changed from the default. REGISTER BIT LABEL ADDRESS 0 ...
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Production Data REGISTER BIT LABEL ADDRESS 3 INPPGAENR 2 INPPGAENL 1 ADCENR 0 ADCENL R3 (03h) 8 OUT4EN 7 OUT3EN 6 LOUT2EN 5 ROUT2EN 4 3 RMIXEN 2 LMIXEN 1 DACENR 0 DACENL 4 (04h) 8 BCP 7 LRP 6:5 ...
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WM8983 REGISTER BIT LABEL ADDRESS 4:3 FMT 2 DLRSWAP 1 ALRSWAP 0 MONO 5 (05h) 8:6 5 WL8 4:3 DAC_COMP 2:1 ADC_COMP 0 LOOPBACK 6 (06h) 8 CLKSEL 7:5 MCLKDIV w DEFAULT DESCRIPTION 10 Audio interface Data Format Select: 00=Right ...
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Production Data REGISTER BIT LABEL ADDRESS 4:2 BCLKDIV (07h) 3 SLOWCLKEN 8 (08h) 5:4 OPCLKDIV 3 GPIO1POL 2:0 GPIO1SEL [2:0] w DEFAULT DESCRIPTION 000 Configures the BCLK output frequency, for use when the chip ...
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WM8983 REGISTER BIT LABEL ADDRESS 9 (09h) 8:7 6 JD_EN 5:4 JD_SEL 3:0 10 (0Ah) 8:7 6 SOFTMUTE 5:4 3 DACOSR128 2 AMUTE 1 DACPOLR 0 DACPOLL 11 (0Bh) 8 DACVU 7:0 DACVOLL 12 (0Ch) 8 DACVU 7:0 DACVOLR w ...
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Production Data REGISTER BIT LABEL ADDRESS 13 (0Dh) 8 7:4 JD_EN1 3:0 JD_EN0 14 (0Eh) 8 HPFEN 7 HPFAPP 6:4 HPFCUT 3 ADCOSR 128 2 1 ADCRPOL 0 ADCLPOL 15 (0Fh) 8 ADCVU 7:0 ADCVOLL 16 (10h) 8 ADCVU 7:0 ...
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WM8983 REGISTER BIT LABEL ADDRESS 18 (12h) 8 EQ3DMODE 7 6:5 EQ1C 4:0 EQ1G 19 (13h) 8 EQ2BW 7 6:5 EQ2C 4:0 EQ2G 20 (14h) 8 EQ3BW 7 6:5 EQ3C 4:0 EQ3G 21 (15h) 8 EQ4BW 7 6:5 EQ4C 4:0 ...
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Production Data REGISTER BIT LABEL ADDRESS 24 (18h) 8 LIMEN 7:4 LIMDCY 3:0 LIMATK 25 (19h) 8:7 6:4 LIMLVL 3:0 LIMBOOST 27 (1Bh) 8 NFU 7 NFEN 6:0 NFA0[13:7] w DEFAULT DESCRIPTION Enable the DAC digital limiter: 0 0=disabled 1=enabled ...
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WM8983 REGISTER BIT LABEL ADDRESS 28 (1Ch) 8 NFU 7 6:0 NFA0[6:0] 29 (1Dh) 8 NFU 7 6:0 NFA1[13:7] 30 (1Eh) 8 NFU 7 6:0 NFA1[6:0] 32 (20h) 8:7 ALCSEL 6 5:3 ALCMAXGAIN 2:0 ALCMINGAIN 33 (21h) 7:4 ALCHLD w ...
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Production Data REGISTER BIT LABEL ADDRESS 3:0 ALCLVL 34 (22h) 8 ALCMODE 7:4 ALCDCY [3:0] 3:0 ALCATK 35 (23h) 8:4 3 NGEN w DEFAULT DESCRIPTION 1011 ALC target – sets signal level at ADC input 1111 : -1.5dBFS 1110 : ...
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WM8983 REGISTER BIT LABEL ADDRESS 2:0 NGTH 36 (24h) 8:5 4 PLL PRESCALE 3:0 PLLN[3:0] 37 (25h) 8:6 5:0 PLLK[23:18] 38 (26h) 8:0 PLLK[17:9] 39 (27h) 8:0 PLLK[8:0] 41 (29h) 8:4 3:0 DEPTH3D 42 (2Ah) 8:6 OUT4_2ADCVOL 5 OUT4_2LNR 43 ...
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Production Data REGISTER BIT LABEL ADDRESS 5 MUTERPGA2INV 4 INVROUT2 3:1 BEEPVOL 0 BEEPEN 44 (2Ch) 8 MBVSEL 7 6 R2_2INPPGA 5 RIN2INPPGA 4 RIP2INPPGA 3 2 L2_2INPPGA 1 LIN2INPPGA 0 LIP2INPPGA 45 (2Dh) 8 INPPGAU 7 INPPGAZCL 6 INPPGAMUTEL ...
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WM8983 REGISTER BIT LABEL ADDRESS 5:0 INPPGAVOLL 46 (2Eh) 8 INPPGAU 7 INPPGAZCR 6 INPPGAMUTER 5:0 INPPGAVOLR 47 (2Fh) 8 PGABOOSTL 7 6:4 L2_2BOOSTVOL 3 2:0 AUXL2BOOSTVOL 48 (30h) 8 PGABOOSTR 7 w DEFAULT DESCRIPTION 010000 Left channel input PGA ...
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Production Data REGISTER BIT LABEL ADDRESS 6:4 R2_2BOOSTVOL 3 2:0 AUXR2BOOSTVOL 49 (31h) 8:7 6 DACL2RMIX 5 DACR2LMIX 3 OUT3BOOST 4 OUT4BOOST 2 SPKBOOST 1 TSDEN 0 VROI 50 (32h) 8:6 AUXLMIXVOL 5 AUXL2LMIX w DEFAULT DESCRIPTION Controls the R2 ...
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WM8983 REGISTER BIT LABEL ADDRESS 4:2 BYPLMIXVOL 1 BYPL2L MIX 0 DACL2L MIX 51 (33h) 8:6 AUXRMIXVOL 5 AUXR2RMIX 4:2 BYPRMIXVOL 1 BYPR2RMIX 0 DACR2RMIX 52 (34h) 8 OUT1VU 7 LOUT1ZC 6 LOUT1MUTE w DEFAULT DESCRIPTION Left bypass volume control ...
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Production Data REGISTER BIT LABEL ADDRESS 5:0 LOUT1VOL 53 (35h) 8 OUT1VU 7 ROUT1ZC 6 ROUT1MUTE 5:0 ROUT1VOL 54 (36h) 8 OUT2VU 7 LOUT2ZC 6 LOUT2MUTE 5:0 LOUT2VOL 55 (37h) 8 OUT2VU 7 ROUT2ZC 6 ROUT2MUTE 5:0 ROUT2VOL 56 (38h) ...
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WM8983 REGISTER BIT LABEL ADDRESS 3 OUT4_2OUT3 2 BYPL2OUT3 1 LMIX2OUT3 0 LDAC2OUT3 57 (39h OUT3_2OUT4 6 OUT4MUTE 5 OUT4ATTN 4 LMIX2OUT4 3 LDAC2OUT4 2 BYPR2OUT4 1 RMIX2OUT4 0 RDAC2OUT4 59 (3Bh) 8:2 1:0 ALCTST 61 (3Dh) 8 ...
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Production Data DIGITAL FILTER CHARACTERISTICS PARAMETER ADC Filter Passband Passband Ripple Stopband Stopband Attenuation Group Delay ADC High Pass Filter High Pass Filter Corner Frequency DAC Filter Passband Passband Ripple Stopband Stopband Attenuation Group Delay Table 71 Digital Filter Characteristics ...
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WM8983 DAC FILTER RESPONSES 20 0 -20 -40 -60 -80 -100 -120 -140 -160 0 0.5 1 Frequency (fs) Figure 54 DAC Digital Filter Frequency Response (128xOSR -20 -40 -60 -80 -100 -120 -140 -160 0 0.5 1 ...
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Production Data HIGHPASS FILTER The WM8983 has a selectable digital highpass filter in the ADC filter path. This filter has two modes, audio and applications. In audio mode the filter applications mode the filter ...
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WM8983 5-BAND EQUALISER The WM8983 has a 5-band equaliser which can be applied to either the ADC path or the DAC path. The plots from Figure 64 to Figure 77 show the frequency responses of each filter with a sampling ...
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Production Data -10 - Frequency (Hz) Figure 69 EQ Band 3 – Peak Filter Centre Frequencies, EQ3BW -10 - ...
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WM8983 -10 - Frequency (Hz) Figure 72 EQ Band 4 – Peak Filter Centre Frequencies, EQ3BW -10 - ...
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Production Data Figure 77 shows the result of having the gain set on more than one channel simultaneously. The blue traces show each band (lowest cut-off/centre frequency) with ±12dB gain. The red traces show the cumulative effect of all bands ...
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WM8983 APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS Figure 78 External Component Diagram w Production Data PD, Rev 4.3, May 2010 122 ...
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Production Data PACKAGE DIAGRAM FL: 32 PIN QFN PLASTIC PACKAGE EXPOSED 6 GROUND PADDLE BOTTOM VIEW A3 C SIDE VIEW SEATING PLANE A3 b Exposed lead Symbols MIN NOM 0.85 ...
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... WM8983 IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice ...