WM8510GEDS/RV Wolfson Microelectronics, WM8510GEDS/RV Datasheet - Page 51

• Manufacturer Part Number: WM8510GEDS/RV
• Description: Audio CODECs VolP MONO CODEC 28-pin
• Manufacturer: Wolfson Microelectronics

Specifications of WM8510GEDS/RV

• Operating Supply Voltage: - 0.3 V to + 7 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-28
• Minimum Operating Temperature: - 25 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Production Data
w
Table 42 Clock Control
LOOPBACK
Setting the LOOPBACK register bit enables digital loopback. When this bit is set the output data
from the ADC audio interface is fed directly into the DAC data input.
COMPANDING
The WM8510 supports A-law and µ-law companding on both transmit (ADC) and receive (DAC)
sides. Companding can be enabled on the DAC or ADC audio interfaces by writing the appropriate
value to the DAC_COMP or ADC_COMP register bits respectively.
R6
Clock
generation
control
REGISTER
ADDRESS
0
4:2
7:5
8
BIT
MS
BCLKDIV
MCLKDIV
CLKSEL
LABEL
0
000
010
1
DEFAULT
Sets the chip to be master over FRAME
and BCLK
0=BCLK and FRAME clock are inputs
1=BCLK and FRAME clock are outputs
generated by the WM8510 (MASTER)
Configures the BCLK and FRAME
output frequency, for use when the chip
is master over BCLK.
000=divide by 1 (BCLK=MCLK)
001=divide by 2 (BCLK=MCLK/2)
010=divide by 4
011=divide by 8
100=divide by 16
101=divide by 32
110=reserved
111=reserved
Sets the scaling for either the MCLK or
PLL clock output (under control of
CLKSEL)
000=divide by 1
001=divide by 1.5
010=divide by 2
011=divide by 3
100=divide by 4
101=divide by 6
110=divide by 8
111=divide by 12
Controls the source of the clock for all
internal operation:
0=MCLK
1=PLL output
PD, Rev 4.5, September 2008
DESCRIPTION
WM8510
51