WM8510GEDS/RV Wolfson Microelectronics, WM8510GEDS/RV Datasheet - Page 72

• Manufacturer Part Number: WM8510GEDS/RV
• Description: Audio CODECs VolP MONO CODEC 28-pin
• Manufacturer: Wolfson Microelectronics

Specifications of WM8510GEDS/RV

• Operating Supply Voltage: - 0.3 V to + 7 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-28
• Minimum Operating Temperature: - 25 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM8510
w
REGISTER
35 (23h)
36 (24h)
37 (25h)
38 (26h)
39 (27h)
40 (28h)
ADDRESS
8:4
3
2:0
8:5
4
3:0
8:6
5:0
8:0
8:0
8:3
2
1
0
BIT
NGEN
NGTH
PLLPRESCALE
PLLN[3:0]
PLLK[23:18]
PLLK[17:9]
PLLK[8:0]
MONOATTN
SPKATTN
LABEL
0
000
1000
001100
01001001
01110100
0010
00000
0000
0
000
1
1
000000
0
0
0
DEFAULT
… (time doubles with every step)
1010 or
higher
ALC attack (gain ramp-down) time
(ALCMODE = 1)
0000
0001
0010
… (time doubles with every step)
1010
Reserved
ALC Noise gate function enable
1 = enable
0 = disable
ALC Noise gate threshold:
000=-39dB
001=-45dB
010=-51db
… (6dB steps)
111=-81dB
Reserved
0 = MCLK input not divided (default)
1 = Divide MCLK by 2 before input PLL
Integer (N) part of PLL input/output frequency ratio.
Use values greater than 5 and less than 13.
Reserved
Fractional (K) part of PLL1 input/output frequency ratio
(treat as one 24-digit binary number).
Fractional (K) part of PLL1 input/output frequency ratio
(treat as one 24-digit binary number).
Fractional (K) part of PLL1 input/output frequency ratio
(treat as one 24-digit binary number).
Reserved
Attenuation control for bypass path (output of input
boost stage) to mono mixer input
0 = 0dB
1 = -10dB
Attenuation control for bypass path (output of input
boost stage) to speaker mixer input
0 = 0dB
1 = -10dB
Reserved
106ms
Per step
22.7us
45.4us
90.8us
23.2ms
DESCRIPTION
852ms
Per 6dB
182.4us
363us
726us
186ms
6.18s
90% of
range
1.31ms
2.62ms
5.23ms
1.34s
PD, Rev 4.5 ,September 2008
Input Limiter /
Automatic Level
Control (ALC)
Input Limiter /
Automatic Level
Control (ALC)
Master Clock
and Phase
Locked Loop
(PLL)
Master Clock
and Phase
Locked Loop
(PLL)
Master Clock
and Phase
Locked Loop
(PLL)
Master Clock
and Phase
Locked Loop
(PLL)
Master Clock
and Phase
Locked Loop
(PLL)
Analogue
Outputs
Analogue
Outputs
Production Data
REFER TO
72