CS48520-CQZ Cirrus Logic Inc, CS48520-CQZ Datasheet
CS48520-CQZ
Specifications of CS48520-CQZ
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CS48520-CQZ Summary of contents
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FEATURES Cost-effective, High-performance 32-bit DSP — 300,000,000 MAC/S (multiply accumulates per second) — Dual MAC cycles per clock — 72-bit accumulators are the most accurate in the industry — 24k x 32 SRAM, 2k blocks - assignable to data or ...
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CS485xx Family Data Sheet 32-bit Audio Decoder DSP Family Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com. IMPORTANT NOTICE Cirrus Logic, Inc. ...
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... Switching Characteristics — Digital Audio Output Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7. Environmental, Manufacturing, & Handling Information . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8. Device Pinout Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.1 CS48520, 48-pin LQFP Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.2 CS48540, 48-pin LQFP Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.3 CS48560,48-pin LQFP Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9. Package Mechanical Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9 ...
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... Figure 8. Direct Stream Digital - Serial Audio Input Timing..................................................................................... 18 Figure 9. Digital Audio Output Port Timing, Master Mode....................................................................................... 19 Figure 10. Digital Audio Output Timing, Slave Mode (Relationship LRCLK to SCLK) ............................................ 19 Figure 11. CS48520, 48-Pin LQFP Pinout .............................................................................................................. 22 Figure 12. CS48540, 48-Pin LQFP Pinout .............................................................................................................. 23 Figure 13. CS48560, 48-Pin LQFP Pinout .............................................................................................................. 24 Figure 14 ...
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... There are three devices comprising the CS485xx family. The CS48520, CS48540 and CS48560 are differentiated by the number of inputs and outputs available. All DSPs support dual input clock domains and dual audio processing paths. All DSPs are available in a 48-pin QFP package. Please ...
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CS485xx Family Data Sheet 32-bit Audio Decoder DSP Family 3. Code Overlays The suite of software available for the CS485xx family consists of an operating system (OS) and a library of overlays. The overlays have been divided into three main ...
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... Table 2. Device and Firmware Selection Guide Device Portable Audio Docking Station CS48520-CQZ Multimedia PC Speakers CS48540-CQZ CS48520 features Plus CS48540-DQZ CS48540 features Plus CS48560-CQZ 12 channel Car Audio CS48560-DQZ Dual Source/Dual Zone 4. Hardware Functional Description 4.1 DSP Core The CS485xx family DSPs are single-core DSP with separate X and Y data and P code memory spaces ...
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... PCM audio on a single data line (the total number possible depends on the ratio of SCLK to LRCLK and the version of chip. For example on the CS48520 only PCM are supported in one line mode and on the CS48560 channels are supported.). ...
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PLL-based Clock Generator The low-jitter PLL generates integer or fractional multiples of a reference frequency which are used to clock the DSP core and peripherals. Through a second PLL divider chain, a dependent clock domain can be output on ...
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CS485xx Family Data Sheet 32-bit Audio Decoder DSP Family 5. Characteristics and Specifications Note: All data sheet minimum and maximum timing parameters are guaranteed over the rated voltage and temperature. All data sheet typical parameters are measured under the following ...
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Power Supply Characteristics (Measurements performed under operating conditions) Parameter Operational Power Supply Current: 1 VDD: Core and I/O operating VDDA: PLL operating VDDIO: With most ports operating Total Operational Power Dissipation: Standby Power Supply Current: VDD: Core and I/O ...
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CS485xx Family Data Sheet 32-bit Audio Decoder DSP Family 5.6 Switching Characteristics— RESET Parameter RESET# minimum pulse width low All bidirectional pins high-Z after RESET# low Configuration pins setup before RESET# high Configuration pins hold after RESET# high RESET# HS[3:0] ...
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Switching Characteristics — Internal Clock Parameter 1 Internal DCLK frequency 1 Internal DCLK period 1. After initial power-on reset dclk the next power-on reset. 5.9 Switching Characteristics — Serial Control Port - SPI Slave Mode Parameter ...
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CS485xx Family Data Sheet 32-bit Audio Decoder DSP Family t spicss SCP_CS# 0 SCP_CLK f spisck A6 SCP_MOSI t spidsu SCP_MISO SCP_IRQ# SCP_BSY# Figure 3. Serial Control Port - SPI Slave Mode Timing 5.10 Switching Characteristics — Serial Control Port ...
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EE_CS# t spicsl 0 SCP_CLK f spisck SCP_MISO A6 t spidsu SCP_MOSI Figure 4. Serial Control Port - SPI Master Mode Timing 5.11 Switching Characteristics — Serial Control Port - I Parameter 1 SCP_CLK frequency SCP_CLK low time ...
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CS485xx Family Data Sheet 32-bit Audio Decoder DSP Family t iicckcmd 0 1 SCP_CLK t iicstscl A6 SCP_SDA t t iicsu iich SCP_IRQ# SCP_BSY# Figure 5. Serial Control Port - I 5.12 Switching Characteristics — Serial Control Port - I ...
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SCP_CLK t iicstscl SCP_SDA iicsu iich Figure 6. Serial Control Port - I 5.13 Switching Characteristics — Digital Audio Slave Input Port Parameter DAI_SCLK period DAI_SCLK duty cycle Setup time DAI_DATAn Hold time ...
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CS485xx Family Data Sheet 32-bit Audio Decoder DSP Family Figure 8. Direct Stream Digital - Serial Audio Input Timing 5.15 Switching Characteristics — Digital Audio Output Port Parameter DAO_MCLK period DAO_MCLK duty cycle DAO_SCLK period for Master or Slave mode ...
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DAO_MCLK DAO_SCLK t daomdv DAOn_DATAn DAO_LRCLK Note: In these diagrams, Falling edge is the inactive edge of DAO_SCLK Figure 9. Digital Audio Output Port Timing, Master Mode t daosstlr DAO_LRCLK DAO_SCLK DAOn_DATAn Note: In these diagrams, Falling edge ...
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... The CS485xx family part number is described as follows: CS485NI-XYZR where N - Product Number Variant I - ROM ID Number X - Product Grade Y - Package Type Z - Lead (Pb) Free R - Tape and Reel Packaging Part No. CS48520-CQZ CS48540-CQZ CS48540-DQZ CS48560-CQZ CS48560-DQZ NOTE: Please contact the factory for availability of the -D (automotive grade) package. 20 Table 3. Ordering Information Grade Temp. Range Commercial 0 to +70 ° ...
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... Environmental, Manufacturing, & Handling Information Table 4. Environmental, Manufacturing, & Handling Information Model Number CS48520-CQZ CS48540-CQZ CS48540-DQZ CS48560-CQZ CS48560-DQZ * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. DS734F3 Peak Reflow Temp MSL Rating* 260 °C 3 Copyright 2009 Cirrus Logic, Inc. CONFIDENTIAL CS485xx Family Data Sheet ...
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... CS485xx Family Data Sheet 32-bit Audio Decoder DSP Family 8. Device Pinout Diagrams 8.1 CS48520, 48-pin LQFP Pinout Diagram VDDIO3 37 38 GPIO8, SCP_CS# GPOI12, SCP_IRQ GNDIO4 41 GPIO13, SCP_BSY#, EE_CS# VDD3 42 43 XTAL_OUT XTI 44 45 XTO GNDA 46 47 PLL_REF_RES VDDA (3.3V CS48520 48-Pin LQFP Figure 11 ...
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CS48540, 48-pin LQFP Pinout Diagram VDDIO3 37 38 GPIO8, SCP_CS# GPOI12, SCP_IRQ GNDIO4 41 GPIO13, SCP_BSY#, EE_CS# VDD3 42 43 XTAL_OUT XTI 44 45 XTO GNDA 46 47 PLL_REF_RES VDDA (3.3V) 48 DS734F3 CS48540 48-Pin LQFP Figure ...
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CS485xx Family Data Sheet 32-bit Audio Decoder DSP Family 8.3 CS48560,48-pin LQFP Pinout Diagram VDDIO3 37 38 GPIO8, SCP_CS# GPOI12, SCP_IRQ# 39 GNDIO4 40 41 GPIO13, SCP_BSY#, EE_CS# 42 VDD3 43 XTAL_OUT XTI 44 45 XTO GNDA 46 47 PLL_REF_RES ...
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Package Mechanical Drawings 9.1 48-pin LQFP Package Drawing MIN A A1 0.05 A2 1. theta 0 L 0.45 L1 NOTES: 1) Reference document: JEDEC MS-026 2) All dimensions are in millimeters and ...
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CS485xx Family Data Sheet 32-bit Audio Decoder DSP Family 10. Revision History Revision Date A1 JUL 2006 A2 JUL 2006 A3 DEC 5 2006 PP1 MAR 12 2007 PP2 December 18, 2007 F1 April 21, 2007 F2 July 14, 2008 ...