CS497024-CVZ Cirrus Logic Inc, CS497024-CVZ Datasheet
CS497024-CVZ
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CS497024-CVZ Summary of contents
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FEATURES Multi-standard 32-bit High Definition Audio Decoding plus Post-Processing Supports high-definition audio formats including: ® — Dolby Digital Plus ® — Dolby TrueHD ® — DTS-HD High Resolution Audio ® — DTS-HD Master Audio ™ — DTS Express Additional Applications ...
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CS4970x4 Data Sheet 32-bit High Definition Audio Decoder DSP Family Table of Contents 1. Documentation Strategy ................................................................................................................ 4 2. Overview .......................................................................................................................................... 4 2.1 Migrating from the CS495xx(2) to the CS4970x4 ........................................................................................... 6 2.2 Licensing ......................................................................................................................................................... 6 3. Code Overlays ................................................................................................................................. ...
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Package Mechanical Drawings ....................................................................................................31 9.1 128-Pin LQFP Package Drawing ..................................................................................................................31 9.2 144-Pin LQFP Package Drawing ..................................................................................................................32 10. Revision History ..........................................................................................................................33 List of Figures Figure 1. RESET# Timing . . . . . . . . . . . . ...
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CS4970x4 Data Sheet 32-bit High Definition Audio Decoder DSP Family 1. Documentation Strategy The CS4970x4 data sheet describes the CS4970x4 family of multichannel audio decoders. This document should be used in conjunction with the following documents when evaluating or designing ...
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... MIPS DTS, DTS-ES, DTS96/24 DTS-HD Master Audio DTS-HD High Resolution Audio CS497024 DTS Express 300 MIPS 1. Processing may be restricted and dependent on firmware selected. Contact your Cirrus Logic FAE for concurrency matrix. 2. Downsampling and Upsampling functionality is located in the operating system. The Cirrus Decimator (Down-Sampler) is also available as a separate post-processing module that is described in the application note, AN288PPI ...
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CS4970x4 Data Sheet 32-bit High Definition Audio Decoder DSP Family 2.1 Migrating from the CS495xx(2) to the CS4970x4 The CS4970x4 was designed to provide an easy upgrade path from the CS495xx & CS4953x. Although 144-pin versions of the two devices ...
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Hardware Functional Description 4.1 Coyote DSP Core The CS4970x4 is a dual-core Coyote DSP with separate X and Y data and P code memory spaces. Each core is a high-performance, 32-bit, user-programmable, fixed-point DSP that is capable of performing ...
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CS4970x4 Data Sheet 32-bit High Definition Audio Decoder DSP Family The port has two independent slave-only clock domains. Each data input can be independently assigned to a clock domain. The sample rate of the input clock domains can be determined ...
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Mode select pins on the CS4970x4 are used to select the boot mode upon the rising edge of reset. A detailed explanation of termination requirements for each communication mode select pin can be found in the CS4970x4 System Designer’s Guide. ...
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CS4970x4 Data Sheet 32-bit High Definition Audio Decoder DSP Family 5. Characteristics and Specifications Note: All data sheet minimum and maximum timing parameters are guaranteed over the rated voltage and temperature. All data sheet typical parameters are measured under the ...
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Parameter Input leakage current (all digital pins with internal pull- up resistors enabled, and XTI) 5.4 Power Supply Characteristics (Measurements performed under operating conditions.) Parameter Power supply current: 1 Core and I/O operating: VDD PLL operating: VDDA With external memory ...
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CS4970x4 Data Sheet 32-bit High Definition Audio Decoder DSP Family 5.7 Switching Characteristics— RESET# Parameter RESET# minimum pulse width low All bidirectional pins high-Z after RESET# low Configuration pins setup before RESET# high Configuration pins hold after RESET# high RESET# ...
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... SCP_BSY# pin should be implemented to prevent overflow of the input data buffer.At boot the maximum speed is Fxtal/3. DS752PP8 Symbol F dclk CS497004-CQZ CS497004-CQZR CS497024-CVZ CS497024-CVZR CS497024-CVZ CS497024-CVZR DCLKP CS497004-CQZ CS497004-CQZR CS497024-CVZ CS497024-CVZR CS497024-CVZ CS497024-CVZR = F . After initial kickstart commands, the PLL is locked to max F dclk xtal Symbol Min f - spisck t 24 spicss t ...
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CS4970x4 Data Sheet 32-bit High Definition Audio Decoder DSP Family t spicss SCP_CS# SCP_CLK f spisck SCP_MOSI SCP_MISO SCP_IRQ# SCP_BSY# Figure 3. Serial Control Port - SPI Slave Mode Timing 5.11 Switching Characteristics — Serial Control Port - SPI Master ...
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EE_CS spicsl SCP_CLK f spisck SCP_MISO A6 t spidsu SCP_MOSI Figure 4. Serial Control Port - SPI Master Mode Timing 5.12 Switching Characteristics — Serial Control Port - I Parameter 1 SCP_CLK frequency SCP_CLK low ...
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CS4970x4 Data Sheet 32-bit High Definition Audio Decoder DSP Family t iicckcmd 0 SCP_CLK t iicstscl A6 SCP_SDA t t iicsu iich SCP_IRQ# SCP_BSY# Figure 5. Serial Control Port - I 5.13 Switching Characteristics — Serial Control Port - I ...
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SCP_CLK t iicstscl SCP_SDA iicsu iich Figure 6. Serial Control Port - I 5.14 Switching Characteristics — Parallel Control Port - Intel Parameter Address setup before PCP_CS# and PCP_RD# low or PCP_CS# and PCP_WR# ...
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CS4970x4 Data Sheet 32-bit High Definition Audio Decoder DSP Family 1. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. Hardware handshaking on the PCP_BSY# pin/bit should ...
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Switching Characteristics — Parallel Control Port - Motorola Parameter Address setup before PCP_CS# and PCP_DS# low Address hold time after PCP_CS# and PCP_DS# low Read Delay between PCP_DS# then PCP_CS# low or PCP_CS# then PCP_DS# low Data valid after ...
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CS4970x4 Data Sheet 32-bit High Definition Audio Decoder DSP Family P C P_A[3: P_AD [7:0] PC P_C P_W P_D P_IR Q # Figure ...
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Switching Characteristics — Digital Audio Slave Input Port Parameter DAI_SCLK period DAI_SCLK duty cycle Setup time DAI_DATAn Hold time DAI_DATAn DAI_SC LK DAI_DATAn Figure 11. Digital Audio Input (DAI) Port Timing Diagram DS752PP8 32-bit High Definition Audio Decoder DSP ...
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CS4970x4 Data Sheet 32-bit High Definition Audio Decoder DSP Family 5.17 Switching Characteristics — DSD Parameter DSD_SCLK Pulse Width Low DSD_SCLK Pulse Width High DSD_SCLK Frequency (64x Oversampled) DSD_A / _B valid to DSD_SCLK rising setup time DSD_SCLK rising to ...
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Switching Characteristics — Digital Audio Output Port Parameter DAO_MCLK period DAO_MCLK duty cycle DAO_SCLK period for Master or Slave mode DAO_SCLK duty cycle for Master or Slave mode Master Mode (Output A1 Mode) DAO_SCLK delay from DAO_MCLK rising edge, ...
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CS4970x4 Data Sheet 32-bit High Definition Audio Decoder DSP Family t daosstlr DAO_LRCLK DAO_SCLK DAOn_DATAn Note: In these diagrams, Falling edge is the inactive edge of DAO_SCLK Figure 14. Digital Audio Output Timing, Slave Mode (Relationship LRCLK to SCLK) 5.19 ...
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SD_CLKOUT t t sdcmdv sdcmdh SD_CS# SD_RAS# SD_CAS# SD_WE# t sddqv SD_DQMn SD_An t sdav t sddsu CAS=2 SD_Dn SD_CLKIN t sdclkl Figure 15. External Memory Interface - SDRAM Burst Read Cycle SD_CLKOUT t t sdcmdv sdcmdh SD_CS# SD_RAS# SD_CAS# ...
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CS4970x4 Data Sheet 32-bit High Definition Audio Decoder DSP Family SD_CLKOUT t sdcmdv SD_CS# SD_RAS# SD_CAS# SD_WE# SD_DQMn SD_An SD_Dn Figure 17. External Memory Interface - SDRAM Auto Refresh Cycle 26 t sdcmdv Copyright 2009 Cirrus Logic t sdcmdh DS752PP8 ...
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SD_CLKOUT SD_CS# SD_RAS# SD_CAS# SD_WE# SD_DQMn SD_An SD_Dn Figure 18. External Memory Interface - SDRAM Load Mode Register Cycle DS752PP8 t t sdcmdv sdcmdh OPCODE Copyright 2009 Cirrus Logic CS4970x4 Data Sheet 32-bit High Definition Audio Decoder DSP Family 27 ...
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... Please contact the factory for availability of the -D (automotive grade) package. Note: 7. Environmental, Manufacturing, and Handling Information Table 5. Environmental, Manufacturing, & Handling Information Model Number CS497004-CQZ CS497004-CQZR CS497014-CVZ CS47014-CVZR CS497024-CVZ CS497024-CVZR * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. 28 Table 4. Ordering Information Grade Temp. Range 0 to +70 °C Commercial Commercial 0 to +70 °C Commercial 0 to +70 ° ...
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Device Pin-Out Diagram 8.1 128-Pin LQFP Pin-Out Diagram GPIO38, PCP_WR# / DS#, SCP2_CLK GPIO11, PCP_A3, AS#, SCP2_MISO / SDA GPIO10, PCP_A2 / A10, SCP2_MOSI GPOI9, SCP1_IRQ# GPIO8, PCP_IRQ#, SCP2_IRQ# GPIO7, SCP1_CS#, IOWAIT GPIO6, PCP_CS#, SCP2_CS# VDDIO7 GNDIO7 GPIO3, DDAC ...
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CS4970x4 Data Sheet 32-bit High Definition Audio Decoder DSP Family 8.2 144-Pin LQFP Pin-Out Diagram GPIO9, PCP_A1 / A9 109 110 GPIO8, PCP_A0 / A8 GPIO7, PCP_AD7 / D7 GPIO6, PCP_AD6 / D6 113 VDDIO7 GPIO5, PCP_AD5 / D5 GPIO4, ...
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Package Mechanical Drawings 9.1 128-Pin LQFP Package Drawing E1 E ∝ L DIM ddd DS752PP8 Figure 21. 128-Pin LQFP Package Drawing Table 6. ...
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CS4970x4 Data Sheet 32-bit High Definition Audio Decoder DSP Family 9.2 144-Pin LQFP Package Drawing Notes: Controlling dimension is millimeter. Dimensioning and tolerancing per ASME Y14.5M-1994. DIM ddd 32 ...
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Revision History Revision Date A1 FEB 2007 PP1 MAY 2007 PP2 JULY 2007 PP3 OCT 2007 PP4 December 20, 2007 PP5 May 28, 2008 PP6 August 4, 2008 PP7 September 30, 2008 PP8 November 6, 2009 DS752PP8 32-bit High ...
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CS4970x4 Data Sheet 32-bit High Definition Audio Decoder DSP Family Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com. IMPORTANT NOTICE “Preliminary” product ...