USB3300-EZK-TR SMSC, USB3300-EZK-TR Datasheet
USB3300-EZK-TR
Specifications of USB3300-EZK-TR
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USB3300-EZK-TR Summary of contents
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... Industrial Operating Temperature -40°C to +85°C 32 pin, QFN lead-free RoHS Compliant package ( 0.90 mm height) Applications The USB3300 is the ideal companion to any ASIC, SoC or FPGA solution designed with a ULPI Hi-Speed USB host, peripheral or OTG core. The USB3300 is well suited for: Cell Phones ...
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... USB3300-EZK for 32 pin, QFN Lead-Free RoHS Compliant Package USB3300-EZK-TR for 32 pin, QFN Lead-Free RoHS Compliant Package (tape and reel) 80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © 2007 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given ...
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... On-The-Go Supplement to the USB 2.0 Specification, Revision 1.0a, June 24, 2003 USB 2.0 Transceiver Macrocell Interface (UTMI) Specification, Version 1.02, May 27, 2000 UTMI+ Specification, Revision 1.0, February 2, 2004 UTMI+ Low Pin Interface (ULPI) Specification, Revision 1.1 SMSC USB3300 3 DATASHEET Revision 1.08 (11-07-07) ...
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... ULPI Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1.3 ULPI Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.1.4 ULPI Register Array 6.1.5 ULPI Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.1.6 ULPI RXD CMD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.1.7 USB3300 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.1.8 USB3300 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.1.9 Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.1.10 Full Speed/Low Speed Serial Modes 6.1.11 Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.2 Hi-Speed USB Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6 ...
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... Figure 6.9 Exiting Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 6.10 USB3300 On-the-Go Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 7.1 USB3300 Application Diagram (Peripheral Figure 7.2 USB3300 Application Diagram (Host or OTG Figure 7.3 USB3300 Application Diagram (Peripheral with Over Voltage Protection Figure 7.4 Expanding Downstream Ports for USB3300 Host Applications . . . . . . . . . . . . . . . . . . . . . . . 50 Figure 8 ...
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... List of Tables Table 3.1 USB3300 Pin Definitions 32-Pin QFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 4.1 Maximum Guaranteed Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 4.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 5.1 Electrical Characteristics: Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 5.2 Electrical Characteristics: CLKOUT Start- Table 5.3 DC Electrical Characteristics: Logic Pins Table 5.4 DC Electrical Characteristics: Analog I/O Pins (DP/DM Table 5 ...
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... Figure 1.1 Basic ULPI USB Device Block Diagram The ULPI interface consists of 12 interface pins; 8 bi-directional data pins, 3 control pins, and a 60 MHz clock. By using the 12 pin ULPI interface the USB3300 is able to provide support for the full range of UTMI+ Level 3 through Level 0, as shown in FS peripheral and as a HS, FS, and LS Host ...
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... Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface ULPI Go devices with 12 pin interface (HS, FS, LS, preamble packet) UTMI+ Level 3 the-Go devices (HS, FS, LS, preamble packet) UTMI+ Level 2 the-Go devices UTMI+ Level 1 and On-the-Go devices (HS and FS Only) UTMI+ Level 0 Hi-Speed Peripherals Only 8 DATASHEET Datasheet USB3300 USB3500 USB3450 USB3280 USB3250 SMSC USB3300 ...
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... Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet Chapter 2 Functional Overview The USB3300 is a highly integrated USB PHY. It contains a complete Hi-Speed USB 2.0 PHY with the ULPI industry standard interface to support fast time to market for a USB product. The USB3300 is composed of the functional blocks shown in described in Chapter 6, " ...
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... Chapter 3 Pin Layout The USB3300 is offered pin QFN package ( 0.9mm). The pin definitions and locations are documented below. 3.1 USB3300 Pin Diagram GND GND CPEN VBUS ID VDD3 Figure 3.1 USB3300 Pin Diagram - Top View The exposed flag of the QFN package must be connected to ground with a via array to the ground plane ...
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... SMSC USB3300 ACTIVE TYPE LEVEL DESCRIPTION I/O, N/A VBUS pin of the USB cable. The USB3300 uses this Analog pin for the Vbus comparator inputs and for Vbus pulsing during session request protocol. Input, N/A ID pin of the USB cable. For non-OTG applications Analog this pin can be floated ...
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... Table 3.1 USB3300 Pin Definitions 32-Pin QFN Package (continued) DIRECTION, PIN NAME 16 VDD3.3 17 DATA[7] 18 DATA[6] 19 DATA[5] 20 DATA[4] 21 DATA[3] 22 DATA[2] 23 DATA[1] 24 DATA[0] 25 VDD3.3 26 VDD1 VDDA1.8 Revision 1.08 (11-07-07) Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface ACTIVE TYPE LEVEL ...
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... Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet Table 3.1 USB3300 Pin Definitions 32-Pin QFN Package (continued) DIRECTION, PIN NAME 30 VDD3.3 31 REG_EN 32 RBIAS GND FLAG SMSC USB3300 ACTIVE TYPE LEVEL DESCRIPTION Power N/A Analog 3.3 volt supply. A 0.1uF low ESR bypass capacitor connected to the ground plane of the PCB is recommended ...
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... Human Body Model EIA/JESD 78, Class II CONDITIONS 14 DATASHEET Datasheet MIN TYP MAX UNITS -0.5 +5.5 V -0.5 2.5 V -0.5 4.0 V -0.5 4.0 V -40 85 ° C -55 150 ° C ± 150 mA MIN TYP MAX UNITS 3.0 3.3 3 DD3.3 0 DD3.3 0.0 5.25 - SMSC USB3300 ...
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... Maximum current numbers are worst case over supply voltage, temperature and process. Table 5.2 Electrical Characteristics: CLKOUT Start-Up PARAMETER SYMBOL Suspend Recovery Time T START Note: The USB330 uses the AutoResume feature, SMSC USB3300 SYMBOL CONDITIONS I Device Unconfigured AVG(UCFG idle not data transfer ...
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... Steady state drive 40.5 TX, RPU disabled 1.0 Bus Idle 0.900 Device Receiving 1.425 14.25 16 DATASHEET Datasheet TYP MAX UNITS 0 DD3.3 0 ± TYP MAX UNITS V 2 0.150 V 0 49.5 Ù MΩ 1.24 1.575 kΩ 2.26 3.09 kΩ 15.0 15.75 kΩ SMSC USB3300 ...
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... Table 5.5 Dynamic Characteristics: Analog I/O Pins (DP/DM) PARAMETER SYMBOL FS Output Driver Timing Rise Time T FSR Fall Time T FFF Output Signal Crossover V CRS Voltage SMSC USB3300 CONDITIONS MIN | V(DP) - V(DM) | 100 -50 Squelch Threshold Un-squelch Threshold 150 45Ω load -10 45Ω load 360 45Ω load ...
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... MIN TYP MAX UNITS 0.2 0.5 0.8 V 0.8 1.4 2.0 V 4.4 4.58 4.75 V 281 340 Ù 656 850 Ù 100 kΩ 80 100 120 kΩ 1 MΩ 240 330 600 kΩ MIN TYP MAX UNITS 1.6 1.8 2 1.6 1.8 2.0 V SMSC USB3300 ...
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... Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet Chapter 6 Architecture Overview The USB3300 architecture can be broken down into the following blocks shown in Figure 6.1, "Simplified USB3300 Architecture" below. Internal VDD3.3 Regulator & POR DATA[7:0] CLKOUT STP ULPI Digital ...
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... Link more cycles to make decisions and reduces the Link complexity. This is the result of the “wrapper less” architecture of the USB3300. This low RxEndDelay should allow legacy UTMI Links to use a “wrapper” to convert the UTMI+ interface to a ULPI interface. ...
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... In Figure 6.2, "ULPI Digital Block Diagram", a single ULPI Protocol Block decodes the ULPI 8-bit bi- directional bus when the Link addresses the PHY. The Link must use the DIR output to determine direction of the ULPI data bus. The USB3300 is the “bus arbitrator”. The ULPI Protocol Block will route data/commands to the transmitter or the ULPI register array. ...
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... ULPI Register Array The USB3300 PHY implements all of the ULPI registers detailed in the ULPI revision 1.1 specification. The complete USB3300 ULPI register set is shown in 8 bits. This table also includes the default states of the register upon POR. The RESET bit in the Revision 1 ...
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... Vendor ID Low: Address = 00h (read only) FIELD NAME BIT Vendor ID Low 7:0 6.1.4.2 Vendor ID High: Address = 01h (read only) FIELD NAME BIT Vendor ID High 7:0 SMSC USB3300 Table 6.3 ULPI Register Map DEFAULT STATE READ 24h 00h 04h 01h 04h 02h ...
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... Automatically clears after reset is complete. 1b Active low PHY suspend. When cleared the PHY will enter Low Power Mode as detailed in Automatically set when exiting Low Power Mode. 0b Driven low. 24 DATASHEET Datasheet DESCRIPTION Table 6.8, "DP/DM termination vs. Section 6.1.9, "Low Power Mode". SMSC USB3300 ...
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... DmPulldown 2 DischrgVbus 3 ChrgVbus 4 SMSC USB3300 DEFAULT 0b Changes the ULPI interface to a 6-pin Serial Mode. The PHY will automatically clear this bit when exiting serial mode. 0b Changes the ULPI interface to a 3-pin Serial Mode. The PHY will automatically clear this bit when exiting serial mode. ...
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... Generate an interrupt event notification when Hostdisconnect changes from high to low. Applicable only in host mode. 1b Generate an interrupt event notification when Vbusvalid changes from high to low. 1b Generate an interrupt event notification when SessValid changes from high to low. 26 DATASHEET Datasheet DESCRIPTION Section 6.5.4, "External DESCRIPTION DESCRIPTION SMSC USB3300 ...
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... HostDisconnect Latch 0 VbusValid Latch 1 SessValid Latch 2 SessEnd Latch 3 IdGnd Latch 4 Reserved 7:5 SMSC USB3300 DEFAULT 1b Generate an interrupt event notification when SessEnd changes from high to low. 1b Generate an interrupt event notification when IdGnd changes from high to low. 0h Driven low. DEFAULT 0b Current value of the UTMI+ Hostdisconnect output. Applicable only in host mode ...
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... ULPI Register Access A command from the Link begins a ULPI transfer from the Link to the USB3300. Anytime the Link wants to write or read a ULPI register, the Link will need to wait until DIR is low, and then send a Transmit Command Byte (TXD CMD) to the PHY. The TXD CMD byte informs the PHY of the type of data being sent. The TXD CMD is followed by the a data transfer to or from the PHY. TXD CMD Byte Encoding" ...
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... PHY is receiving data from the Link. STP is used to end the transaction and data is registered after the de-assertion of STP. After the write operation completes, the Link must drive a ULPI Idle (00h) on the data bus or the USB3300 may decode the bus value as a ULPI command. SMSC USB3300 ...
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... When a USB Receive is occurring RXD CMDs are sent when ever NXT = 0 and DIR = 1. When a USB Transmit occurs the RXD CMDs are returned to the Link after the STP is asserted ending the Link to USB3300 transfer of the bytes to be sent on the transmit. To summarize a RXD CMD transfer occurs: when DIR is low and a linestate change occurs ...
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... USB3300 Transmitter The USB3300 ULPI transmitter fully supports HS, FS, and LS transmit operations. Figure 6.2, "ULPI Digital Block Diagram" shows the high speed, full speed, and low speed transmitter block controlled by ULPI Protocol Block. Encoding of the USB packet follows the bit-stuffing and NRZI outlined in the USB 2 ...
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... USB3300, when operating as a host, will transmit DP/DM. The transmitters will end the K with SE0 for two Low Speed bit times. If the USB3300 was operating in high speed mode before the suspend, the host must change to high speed mode before the SE0 ends. SE0 is two low speed bit times which is about 1 ...
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... DP/DM SE0 During transmit the PHY will use NXT to control the rate of data flow into the PHY. If the USB3300 pipeline is full or bit-stuffing causes the data pipeline to overfill NXT is de-asserted and the Link will hold the value on Data until NXT is asserted. The USB Transmit ends when the Link asserts STP while NXT is asserted ...
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... DIR high, the RXD CMD is driven on the data bus. In full speed, the USB3300 will not issue a Rxactive de-assertion in the RXD CMD until the DP/DM linestate transition to idle. This prevents the Link from violating the two full speed bit times minimum turn around time ...
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... SessEnd comparators can have their interrupts masked to lower the suspend current. Refer to Section 6.1.9.4, "Minimizing Current in Low Power While in Low Power Mode, the Data bus is driven asynchronously because all of the PHY clocks are stopped during Low Power Mode. SMSC USB3300 ...
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... Exiting Low Power Mode To exit Low Power Mode, the Link will assert STP. Upon the assertion of STP, the USB3300 will begin its start-up procedure. After the PHY start-up is complete, the PHY will start the clock on CLKOUT and de-assert DIR. Once DIR has been de-asserted, the Link can de-assert STP when ready and start operating in Synchronous Mode ...
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... In some cases, a Link may be software configured and not have control of its STP pin until after the PHY has started. In this case, the USB3300 has an internal pull-up on the STP input pad which will pull STP high while the Link’s STP output is tri-stated. The STP pull-up resistor is enabled on POR and can be disabled by setting the InterfaceProtectDisable bit 7 of the Interface Control register. The STP pull-up resistor will pull-up the Link’ ...
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... Reset Pin The reset input of the USB3300 may be asynchronously asserted and de-asserted so long held in the asserted state continuously for a duration greater than one clkout clock cycle. The reset input may be asserted when the USB3300 clkout signal is not active (i.e. in the suspend state caused by asserting the SuspendM bit) but reset must only be de-asserted when the USB3300 clkout signal is active and the reset has been held asserted for a duration greater than one clkout clock cycle ...
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... Host HS/FS Resume Host low Speed Host LS Suspend Host LS Resume Host Test J/Test_K Peripheral Settings Peripheral Chirp Peripheral HS Peripheral FS Peripheral HS/FS Suspend Peripheral HS/FS Resume Peripheral LS Peripheral LS Suspend SMSC USB3300 Table 6.8, "DP/DM termination vs. Signaling REGISTER SETTINGS XXb Xb 01b Xb Xb 01b 0b 00b 1b 1b ...
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... The USB3300 uses an internal crystal driver and PLL sub-system to provide a clean 480MHz reference clock that is used by the PHY during both transmit and receive. The USB3300 requires a clean 24MHz crystal or clock as a frequency reference. If the 24MHz reference is noisy or off frequency the PHY may not operate correctly ...
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... Internal Regulators and POR The USB3300 includes an integrated set of built in power management functions, including a POR generator. Internal regulators enable the USB3300 to be powered from a single 3.3 volt power supply, thereby reducing the bill of materials and simplifying product design. 6.4.1 Internal Regulators The USB3300 has two internal regulators that create two 1 ...
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... A B PERIPHERAL The USB3300 provides an integrated pull-up resistor and a comparator to detect if the ID pin is floating or grounded. An integrated pull-up resistor is provided to pull the ID pin high to VDD3.3 when a Mini- B plug is inserted and the cable is floating. When a Mini-A plug is connected, the pull-up resistor will Revision 1.08 (11-07-07) Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface 0 ...
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... A-device can provide 100-500mA on Vbus it must ensure that Vbus does not go below 4.75 volts. The internal Vbus comparator is designed to ensure that Vbus remains above 4.4 volts. If the design is required to supply over 100mA the USB3300 provides an input for a more accurate Vbus comparator or fault (over current) detection described in SMSC USB3300 Table 5.6, " ...
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... Driving External Vbus When a system is operating as a host required to source 5 volts on VBUS. The USB3300 fully supports VBUS power control using external devices. The USB3300 provides an active high control signal, CPEN, which is dedicated to controlling the Vbus supply when configured as an A-Device. The ...
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... The EXTVBUS pin has a built in pull down resistor that is controlled by the UseExternalVbusIndicator bit [7] of the OTG control register. When UseExternalVbusIndicator is set to 0 (default) the pull down resistor is activated to prevent the pin from floating when it is unused. When UseExternalVbusIndicator is set to 1 the pull down resistor is disconnected. SMSC USB3300 INDICATOR INDICATOR PASS THRU ...
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... VBUS and GND pins of the USB connector is used as the source of system power. The USB2.0 standard restricts the voltage at the VBUS pin to a maximum value of 5.25V. In some applications, it may be required to provide protection to the USB3300 VBUS pin if the VBUS voltage exceeds the USB2.0 specifications. ...
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... The capacitor C VBUS must be installed on Supply this side VBUS USB C Receptacle VBUS 1 VBUS SHIELD GND C DC_BLOCK Figure 7.1 USB3300 Application Diagram (Peripheral) SMSC USB3300 USB3300 DATA7 DATA6 DATA5 DATA4 DATA3 VBUS DATA2 4 VBUS DATA1 DATA0 STP 31 REG_EN NXT DIR 30 VDD3.3 CLKOUT ...
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... R . VBUS USB C Receptacle 1 VBUS SHIELD GND Figure 7.2 USB3300 Application Diagram (Host or OTG) Revision 1.08 (11-07-07) Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface USB3300 3 CPEN DATA7 DATA6 DATA5 DATA4 10 EXTVBUS DATA3 DATA2 4 VBUS DATA1 ...
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... VBUS must be installed on Supply this side VBUS USB C VBUS Receptacle 1 VBUS SHIELD GND C DC_BLOCK Figure 7.3 USB3300 Application Diagram (Peripheral with Over Voltage Protection) SMSC USB3300 USB3300 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 4 VBUS DATA1 DATA0 STP 31 REG_EN NXT DIR 30 VDD3.3 ...
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... Link ASIC and the hub can be placed on a separate board next to the USB ports. The only data connection required between the boards is DP and DM. The CPEN output of the USB3300 is optional and can be used to turn the Hub on or off to lower current when the USB connection isn’t needed. ...
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... HBM testing verifies the ability to withstand the ESD strikes like those that occur during handling and manufacturing, and is done without power applied to the IC. To pass the test, the device must have no change in operation or performance due to the event. All pins on the USB3300 provide protection. ...
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... Chapter 8 Package Outline The USB3300 is offered in a compact 32 pin lead-free QFN package. Figure 8.1 USB3300-EZK 32 Pin QFN Package Outline 0.9 mm Body (Lead-Free) Table 8.1 32 Terminal QFN Package Parameters MIN NOMINAL A 0. 0.20 REF D 4.85 D1 4.55 D2 3.15 E 4.85 E1 4.55 E2 3.15 L 0.30 e 0.50 BSC b 0 ...
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... Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet Figure 8.1 QFN, 5x5 Taping Dimensions and Part Orientation SMSC USB3300 53 DATASHEET Revision 1.08 (11-07-07) ...
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... Figure 8.2 Reel Dimensions for 12mm Carrier Tape Revision 1.08 (11-07-07) Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface 54 DATASHEET Datasheet SMSC USB3300 ...
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... Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet Figure 8.3 Tape Length and Part Quantity Note: Standard reel size is 4000 pieces per reel. SMSC USB3300 55 DATASHEET Revision 1.08 (11-07-07) ...