FM25V02-G Ramtron, FM25V02-G Datasheet
FM25V02-G
Specifications of FM25V02-G
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FM25V02-G Summary of contents
Page 1
... Serial Flash can cause data loss. The FM25V02 provides substantial benefits to users of Serial Flash as a hardware drop-in replacement. The devices use the high-speed SPI bus, which enhances the high-speed write capability of F-RAM technology ...
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... Q may be connected to D for a single pin data interface. VDD Supply Power Supply VSS Supply Ground Rev. 2.0 May 2010 4096 x 64 FRAM Array 15 Data I/O Register 3 Nonvolatile Status Register Figure 1. Block Diagram spec, pg 11). However not used specifications. DD FM25V02 - 256Kb SPI FRAM 8 Q Page ...
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... This is explained in more detail in the interface section. Users expect several obvious system benefits from the FM25V02 due to its fast write cycle and high endurance as compared to Serial Flash. In addition there are less obvious benefits as well. For example ...
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... System Hookup The SPI interface uses a total of four pins: clock, data-in, data-out, and chip select. A typical system configuration uses one or more FM25V02 devices with a microcontroller that has a dedicated SPI port, as Figure 3 illustrates. Note that the clock, data-in, and data-out pins are common among all devices. ...
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... Power Up to First Access The FM25V02 is not accessible for a period of time (t ) after power up. Users must comply with the PU timing parameter t , which is the minimum time PU from V (min) to the first /S low. DD Data Transfer All data transfers to and from the FM25V02 occur in 8-bit groups. They are synchronized to the clock signal (C), and they transfer most significant bit (MSB) first ...
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... Status Register & Write Protection The write protection features of the FM25V02 are multi-tiered. Taking the /W pin to a logic low state is the hardware write-protect function. Status Register write operations are blocked when /W is low. To write the memory with /W high, a WREN op-code must first be issued. Assuming that writes are enabled using WREN and by /W, writes to memory are controlled by the Status Register ...
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... The SPI interface, which is capable of a relatively high clock frequency, highlights the fast write capability of the F-RAM technology. Unlike Serial Flash, the FM25V02 can perform sequential writes at bus speed. No page buffer is needed and any number of sequential writes may be performed. Write Operation All writes to the memory array begin with a WREN op-code ...
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... Figure 10. Memory Read with 2-Byte Address op-code Figure 11. Fast Read with 2-Byte Address and Dummy Byte Rev. 2.0 May 2010 15-bit Address 15-bit Address MSB 15-bit Address Dummy byte MSB LSB FM25V02 - 256Kb SPI FRAM ata LSB MSB LSB Dat a MSB MSB Dat Page LSB 7 ...
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... Device ID The FM25V02 and FM25VN02 devices can be interrogated for its manufacturer, product identification, and die revision. The RDID op-code 9Fh allows the user to read the manufacturer ID and product ID, both of which are read-only bytes. The JEDEC-assigned manufacturer ID places the Ramtron identifier in bank 7, therefore there are six bytes of the continuation code 7Fh followed by the single byte C2h ...
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... The function (shown below) is used to calculate the CRC value. To perform the calculation, 7 bytes of data are filled into a memory buffer in the same order as they are read from the part – i.e. byte7, byte6, byte5, byte4, byte3, byte2, byte1 of the serial number. The ...
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... S C C3h D Q Byte 7 Endurance The FM25V02 and FM25VN02 devices are capable 14 of being accessed at least 10 times, reads or writes. An F-RAM memory operates with a read and restore mechanism. Therefore, an endurance cycle is applied on a row basis for each access (read or write) to the memory array. The F-RAM architecture is based on an array of rows and columns ...
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Electrical Specifications Absolute Maximum Ratings Symbol Description V Power Supply Voltage with respect Voltage on any pin with respect Storage Temperature STG T Lead Temperature (Soldering, 10 seconds) LEAD V Electrostatic Discharge ...
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... Input and output timing levels 0.5 V Output Load Capacitance 30 pF Serial Data Bus Timing Rev. 2.0 May 2010 = 30pF, unless otherwise specified 2.0 to 2.7V DD Min Max 3.3V) DD Min - - DD DD FM25V02 - 256Kb SPI FRAM V 2.7 to 3.6V DD Min Max Units Notes 0 40 MHz 2 2 ...
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... Recovery Time from Sleep Mode REC Notes 1. This parameter is characterized and not 100% tested. 2. Slope measured at any point Rev. 2.0 May 2010 min -40° 85° 2.0V to 3.6V, unless otherwise specified) DD min) DD waveform. FM25V02 - 256Kb SPI FRAM Min Max Units Notes 50 - µ s/V ...
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... R=rev code, LLLLLLL= lot code XXXXXX-P RIC=Ramtron Int’l Corp, YY=year, WW=work week RLLLLLLL RICYYWW Examples: FM25V02, “Green”/RoHS SOIC package, Rev. A, Lot 9646447, Year 2010, Work Week 11 Without S/N feature FM25V02-G A9646447 RIC1011 Rev. 2.0 May 2010 Recommended PCB Footprint 3.90 0.10 6 ...
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... May 2010 Exposed metal pad should be left floating. 0.0 - 0.05 Recommended PCB Footprint 0.20 REF. 0.60 0.40 ±0.05 Silkscreen Pin 1 0.95 With S/N feature RG5VN02 0003 0939 FM25V02 - 256Kb SPI FRAM 3.60 ±0.10 Pin 1 ID 2.85 REF 0.30 ±0.1 4.30 0.50 Page ...
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... Revision History Revision Date 0.1 3/24/2009 1.0 10/6/2009 2.0 5/25/2010 Ordering Information Part Number Features FM25V02-G Device ID FM25VN02-G Device ID, S/N FM25V02-GTR Device ID FM25VN02-GTR Device ID, S/N FM25V02-DG Device ID FM25VN02-DG Device ID, S/N FM25V02-DGTR Device ID FM25VN02-DGTR Device ID, S/N Rev. 2.0 May 2010 Summary Initial release. ...