S29GL01GP12TFI010 Spansion Inc., S29GL01GP12TFI010 Datasheet - Page 35

• Manufacturer Part Number: S29GL01GP12TFI010
• Description: Flash 3V 1 Gb Mirrorbit highest address120ns
• Manufacturer: Spansion Inc.

Specifications of S29GL01GP12TFI010

• Memory Type: NOR
• Memory Size: 1 Gbit
• Access Time: 110 ns
• Data Bus Width: 8 bit, 16 bit
• Architecture: Uniform
• Interface Type: Page-mode
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 50 mA
• Mounting Style: SMD/SMT
• Operating Temperature: + 85 C
• Package / Case: TSOP-56
• Memory Configuration: 128K X 16
• Ic Interface Type: Parallel
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: BGA
• No. Of Pins: 56
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

November 28, 2007 S29GL-P_00_A8
7.7.7
7.7.8
Accelerated Program
Unlock Bypass
Accelerated single word programming and write buffer programming operations are enabled through the
WP#/ACC pin. This method is faster than the standard program command sequences.
Note
The accelerated program functions must not be used more than 10 times per sector.
If the system asserts V
mode and uses the higher voltage on the input to reduce the time required for program operations. The
system can then use the Write Buffer Load command sequence provided by the Unlock Bypass mode. Note
that if a “Write-to-Buffer-Abort Reset” is required while in Unlock Bypass mode, the full 3-cycle RESET
command sequence must be used to reset the device. Removing V
of the embedded program operation, returns the device to normal operation.
This device features an Unlock Bypass mode to facilitate shorter programming commands. Once the device
enters the Unlock Bypass mode, only two write cycles are required to program data, instead of the normal
four cycles.
This mode dispenses with the initial two unlock cycles required in the standard program command sequence,
resulting in faster total programming time. The
the unlock bypass command sequences.
During the unlock bypass mode, only the Read, Program, Write Buffer Programming, Write-to-Buffer-Abort
Reset, and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must
issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the sector address
and the data 90h. The second cycle need only contain the data 00h. The sector then returns to the read
mode.
Software Functions and Sample Code
The following are C source code examples of using the unlock bypass entry, program, and exit functions.
Refer to the Spansion Low Level Driver User’s Guide (available soon on www.spansion.com) for general
information on Spansion Flash memory software development guidelines.
Cycle
Sectors must be unlocked prior to raising WP#/ACC to V
The WP#/ACC pin must not be at V
damage may result.
It is recommended that WP#/ACC apply V
recommended that WP#/ACC apply from V
/* Example: Unlock Bypass Entry Command
1
2
3
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x555 ) = 0x0020;
/* At this point, programming only takes two write cycles.
/* Once you enter Unlock Bypass Mode, do a series of like
/* operations (programming or sector erase) and then exit
/* Unlock Bypass Mode before beginning a different type of
/* operations.
D a t a
S h e e t
Entry Command
HH
Description
on this input, the device automatically enters the aforementioned Unlock Bypass
Unlock
Unlock
S29GL-P MirrorBit
(LLD Function = lld_UnlockBypassEntryCmd)
( P r e l i m i n a r y )
Table 7.14 Unlock Bypass Entry
HH
for operations other than accelerated programming, or device
HH
HH
Command Definitions on page 66
®
after power-up sequence is completed. In addition, it is
*/
Flash Family
to V
Operation
/* write unlock cycle 1
/* write unlock cycle 2
/* write unlock bypass command
IH
Write
Write
Write
/V
IL
HH
before powering down V
.
HH
Word Address
*/
*/
*/
*/
*/
Base + 2AAh
Base + 555h
Base + 555h
from the ACC input, upon completion
shows the requirements for
CC
/V
IO
*/
*/
*/
.
00AAh
0055h
0020h
Data
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