S29GL01GP12TFI010 Spansion Inc., S29GL01GP12TFI010 Datasheet - Page 39

• Manufacturer Part Number: S29GL01GP12TFI010
• Description: Flash 3V 1 Gb Mirrorbit highest address120ns
• Manufacturer: Spansion Inc.

Specifications of S29GL01GP12TFI010

• Memory Type: NOR
• Memory Size: 1 Gbit
• Access Time: 110 ns
• Data Bus Width: 8 bit, 16 bit
• Architecture: Uniform
• Interface Type: Page-mode
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 50 mA
• Mounting Style: SMD/SMT
• Operating Temperature: + 85 C
• Package / Case: TSOP-56
• Memory Configuration: 128K X 16
• Ic Interface Type: Parallel
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: BGA
• No. Of Pins: 56
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

November 28, 2007 S29GL-P_00_A8
7.8.5
7.8.6
7.8.7
DQ5: Exceeded Timing Limits
DQ3: Sector Erase Timeout State Indicator
DQ1: Write to Buffer Abort
this toggling behavior to be properly observed, the consecutive status bit reads must not be interleaved with
read accesses to other memory sectors. If it is not possible to temporarily prevent reads to other memory
sectors, then it is recommended to use the DQ7 status bit as the alternative method of determining the active
or inactive status of the write operation.
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a “1,” indicating that the program or erase cycle was not successfully
completed. The device does not output a 1 on DQ5 if the system tries to program a 1 to a location that was
previously programmed to 0. Only an erase operation can change a 0 back to a 1. Under this condition, the
device ignores the bit that was incorrectly instructed to be programmed from a 0 to a 1, while any other bits
that were correctly requested to be changed from 1 to 0 are programmed. Attempting to program a 0 to a 1 is
masked during the programming operation. Under valid DQ5 conditions, the system must write the reset
command to return to the read mode (or to the erase-suspend-read mode if a sector was previously in the
erase-suspend-program mode).
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not
erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors
are selected for erasure, the entire time-out also applies after each additional sector erase command. When
the time-out period is complete, DQ3 switches from a “0” to a “1.” If the time between additional sector erase
commands from the system can be assumed to be less than t
See
After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6
(Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is
“1,” the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored
until the erase operation is complete. If DQ3 is “0,” the device accepts additional sector erase commands. To
ensure the command has been accepted, the system software should check the status of DQ3 prior to and
following each sub-sequent sector erase command. If DQ3 is high on the second status check, the last
command might not have been accepted.
DQ1 indicates whether a Write to Buffer operation was aborted. Under these conditions DQ1 produces a “1”.
The system must issue the “Write to Buffer Abort Reset” command sequence to return the device to reading
array data. See
Sector Erase on page 30
D a t a
Write Buffer Programming on page 26
S h e e t
S29GL-P MirrorBit
for more details.
( P r e l i m i n a r y )
Table 7.17
®
Flash Family
shows the status of DQ3 relative to the other status bits.
for more details.
SEA
, then the system need not monitor DQ3.
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