S29GL256P11TFI010 Spansion Inc., S29GL256P11TFI010 Datasheet - Page 65

• Manufacturer Part Number: S29GL256P11TFI010
• Description: Flash 3V 256Mb Mirrorbit highest address110ns
• Manufacturer: Spansion Inc.

Specifications of S29GL256P11TFI010

• Memory Type: NOR
• Memory Size: 256 Mbit
• Access Time: 110 ns
• Data Bus Width: 8 bit, 16 bit
• Architecture: Uniform
• Interface Type: Page-mode
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 50 mA
• Mounting Style: SMD/SMT
• Operating Temperature: + 85 C
• Package / Case: TSOP-56
• Memory Configuration: 128K X 16
• Ic Interface Type: Parallel
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: TSOP
• No. Of Pins: 56
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Legend
X = Don’t care
RD(0) = Read data.
SA = Sector Address. Address bits A
PWD = Password
PWD
Data = Lock Register Contents: PD(0) = Secured Silicon Sector Protection Bit, PD(1) = Persistent Protection Mode Lock Bit, PD(2) = Password Protection Mode
Lock Bit.
Notes
1. See
2. All values are in hexadecimal.
3. All bus cycles are write cycles unless otherwise noted.
4. Data bits DQ15-DQ8 are don’t cares for unlock and command cycles.
5. Address bits A
6. All Lock Register bits are one-time programmable. Program state = “0” and the erase state = “1.” The Persistent Protection Mode Lock Bit and the Password
7. The Exit command returns the device to reading the array.
8. If any Command Set Entry command was written, an Exit command must be issued to reset the device into read mode.
9. For PWDx, only one portion of the password can be programmed per each “A0” command.
10. Note that the password portion can be entered or read in any order as long as the entire 64-bit password is entered or read.
11. If ACC = V
12. Protected State = “00h,” Unprotected State = “01h.”
13. The All PPB Erase command embeds programming of all PPB bits before erasure.
November 21, 2006 S29GL-P_00_A3
Protection Mode Lock Bit cannot be programmed at the same time or the Lock Register Bits Program operation aborts and returns the device to read mode. Lock
Register bits that are reserved for future use default to “1’s.” The Lock Register is shipped out as “FFFF’s” before Lock Register Bit program execution.
x
= Password word0, word1, word2, and word3.
Command Set Entry
Program
Read
Command Set Exit (7, 8)
Command Set Entry
Password Program
Password Read
Password Unlock
Command Set Exit (7, 8)
PPB Command Set Entry
PPB Program (11, 12)
All PPB Erase
PPB Status Read
PPB Command Set Exit (7, 8)
PPB Lock Command Set Entry
PPB Lock Set
PPB Lock Status Read
PPB Lock Command Set Exit (7, 8)
DYB Command Set Entry
DYB Set (11, 12)
DYB Clear
DYB Status Read
DYB Command Set Exit (7, 8)
Table 7.1 on page 14
(6)
HH
Command (Notes)
(6)
, sector protection matches when ACC = V
MAX
(12)
(12)
:A16 are don’t cares for unlock and command cycles, unless SA or PA required. (A
(13)
(10)
(10)
(12)
(12)
(9)
D a t a
for description of bus operations.
(12)
max
Table 12.2 S29GL-P Sector Protection Command Definitions, x16
–A16 uniquely select any sector.
S h e e t
3
2
1
2
3
2
4
7
2
3
2
2
1
2
3
2
1
2
3
2
2
1
2
( A d v a n c e
First/Seventh
Addr
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
555
77h
555
555
555
555
SA
SA
00
00
00
IH
S29GL-P MirrorBit
.
RD (0)
RD (0)
RD (0)
PWD0
DATA
Data
AA
A0
AA
A0
AA
A0
AA
A0
AA
A0
A0
90
25
29
90
80
90
90
90
PWA x
Addr
XXX
XXX
XXX
XXX
XXX
XXX
XXX
2AA
2AA
2AA
2AA
2AA
SA
SA
SA
01
00
00
Second
I n f o r m a t i o n )
TM
PWD 1
PWD x
DATA
Data
Flash Family
55
00
55
03
00
55
00
30
00
55
00
00
55
00
01
00
Addr
555
555
555
555
555
02
00
Bus Cycles (Notes 1–5)
Third
PWD
PWD
Data
MAX
C0
E0
40
60
50
2
0
is the Highest Address pin.)
Addr
03
01
Fourth
PWD 3
PWD 1
Data
Addr
02
Fifth
PWD
Data
2
Addr
03
Sixth
PWD 3
Data
63