ispPAC-POWR1220AT8-02TN100I Lattice, ispPAC-POWR1220AT8-02TN100I Datasheet
ispPAC-POWR1220AT8-02TN100I
Specifications of ispPAC-POWR1220AT8-02TN100I
Available stocks
Related parts for ispPAC-POWR1220AT8-02TN100I
ispPAC-POWR1220AT8-02TN100I Summary of contents
Page 1
... E nology. The ispPAC-POWR1220AT8 device provides 12 independent analog input channels to monitor power supply test points. Each of these input channels offers a differential input to support remote ground ...
Page 2
... Builder™, an easy-to-learn language integrated into the PAC-Designer monitor the status of any of the analog input channel comparators or the digital inputs. In addition to the sequence control functions, the ispPAC-POWR1220AT8 incorporates eight DACs for generating trimming voltage to control the output voltage of a DC-DC converter. The trimming voltage can be set to four hard- ware selectable preset values (voltage profiles) or can be dynamically loaded in to the DAC through the I Additionally, each power supply output voltage can be maintained typically within 0 ...
Page 3
... Source 100µA to 3000µA Sink 1-3 ispPAC-POWR1220AT8 Data Sheet Description Trim Select Input 0 Registered by MCLK Trim Select Input 1 Registered by MCLK PLD Logic Input 1 Registered by MCLK PLD Logic Input 2 Registered by MCLK PLD Logic Input 3 Registered by MCLK ...
Page 4
... DAC Offset -320mV to +320mV from Programmable DAC Offset -320mV to +320mV from Programmable DAC Offset 1-4 ispPAC-POWR1220AT8 Data Sheet Description Open-Drain Output 2 High-voltage FET Gate Driver 2 Open-Drain Output 3 High-voltage FET Gate Driver 3 Open-Drain Output 4 High-voltage FET Gate Driver 4 Open-Drain Output 5, (SMBUS Alert Active ...
Page 5
... VCCD and VCCA pins must be connected together on the circuit board. 8. GNDA and GNDD pins must be connected together on the circuit board. 9. The RESETb pin should only be used for cascading two or more ispPAC-POWR1220AT8 devices. 10. The VCCPROG pin MUST be left floating when VCCD and VCCA are powered. ...
Page 6
... CCD CCA V and V not powered CCD CCA pins pins OUT[5:20] pins HVOUT[1:4] pins in open-drain mode Power applied ESD Stress Min. HBM 2000 CDM 1000 1-6 ispPAC-POWR1220AT8 Data Sheet Min. Max. -0.5 4.5 -0.5 4.5 -0.5 6 -0.5 6 -0.5 4 -0.5 6 -0.5 6 -0.5 6 -0.5 13 ...
Page 7
... V Gate driver output voltage PP Gate driver source current I OUTSRC (HIGH state) Gate driver sink current I OUTSINK (LOW state) 1. 12V setting only available on the ispPAC-POWR1220AT8-02. Conditions During programming cycle supplies. Conditions 1 range, operating temperature, process. CCA Conditions 1 12V setting 10V setting ...
Page 8
... This is the total resultant error in the trimmed power supply output voltage referred to any DAC code due to the DAC’s INL, DNL, gain, out- put impedance, offset error and bipolar offset error across the industrial temperature range and the ispPAC-POWR1200AT8 operating V and V ranges ...
Page 9
... Threshold below which RESETb is LOW TL V Threshold above which RESETb is HIGH TH V Threshold above which RESETb is valid T Capacitive load on RESETb for master/slave C L operation 1. Corresponds to VCCA and VCCD supply voltages. Figure 1-2. ispPAC-POWR1220ATE Power-On Reset Reset State ispPAC-POWR1220AT8 Data Sheet Conditions 1 1 ...
Page 10
... Spacing between available Resolution adjacent timer intervals Accuracy Timer accuracy Over Recommended Operating Conditions Conditions f = 8MHz CLK f = 8MHz CLK f = 8MHz CLK 1-10 ispPAC-POWR1220AT8 Data Sheet Min. Typ. Max 7.6 8 8.4 7.2 8.8 250 0.032 1966 13 -6.67 -12.5 Units µ ...
Page 11
... ATDI, TDISEL, 2.5V supply SCL, SDA IN[1: 10mA SINK I = 20mA SINK I = 4mA SINK I = 4mA SRC ; IN[1:6] referenced TDO, TDI, TMS, ATDI, TDISEL referenced to V CCD CCINP 1-11 ispPAC-POWR1220AT8 Data Sheet Min. Typ. Max. +/- 0.8 0.7 30% V CCD 30% V CCINP 2.0 1.7 70 CCD CCD 70% V ...
Page 12
... T minimum time after a convert request is made is the only way to guarantee a valid conversion is ready for CONVERT readout. When F is greater than 50kHz, ADC conversion complete is ensured by waiting for the DONE status bit. I2C ispPAC-POWR1220AT8 Data Sheet Definition 1-12 100KHz 400KHz Min. ...
Page 13
... VIL State Update-IR Conditions SU1 CKH Select-DR Scan SU1 H SU1 CKL PWP CKH Run-Test/Idle (Program) Select-DR Scan 1-13 ispPAC-POWR1220AT8 Data Sheet Min. Typ. Max. 10 — — 30 — — 30 — — 200 — — — — 15 — — — — 10 — — 20 — ...
Page 14
... Theory of Operation Analog Monitor Inputs The ispPAC-POWR1220AT8 provides 12 independently programmable voltage monitor input circuits as shown in Figure 1-7. Two individually programmable trip-point comparators are connected to an analog monitoring input. Each comparator reference has 368 programmable trip points over the range of 0.664V to 5.734V. Additionally, a 75mV ‘ ...
Page 15
... VMONxGS (to sense the power supply ground). Differential voltage sensing minimizes inaccuracies in voltage measurement with ADC and monitor thresholds due to the potential difference between the ispPAC-POWR1220AT8 device ground and the ground potential at the sensed node on the circuit board. The voltage output of the differential input buffer is monitored by two individually programmable trip-point compara- tors, shown as CompA and CompB. Table 1-1 shows all 368 trip points spanning the range 0.664V to 5.734V to which a comparator’ ...
Page 16
... To monitor under-voltage fault conditions, the LTP should be used. Tables 1 and 2 show both the under-voltage and over-voltage trip points, which are automatically selected in soft- ware depending on whether the user is monitoring for an over-voltage condition or an under-voltage condition. UTP LTP 1-16 ispPAC-POWR1220AT8 Data Sheet (a) (b) ...
Page 17
... Data Sheet 2.665 3.156 3.758 4.818 2.650 3.139 3.738 4.792 2.636 3.123 3.718 4.766 2.622 3.106 3.698 4.741 2.607 3 ...
Page 18
... Low-V Sense ispPAC-POWR1220AT8 Data Sheet Coarse Range Setting 1.326 1.571 1.874 2.232 1.319 1.563 1.864 2.220 1.312 1.554 1.854 2.209 1.305 1.546 1.844 2.197 1.298 1 ...
Page 19
... The third section in the ispPAC-POWR1220AT8’s input voltage monitor is a digital filter. When enabled, the compar- ator output will be delayed by a filter time constant of 64 µS, and is especially useful for reducing the possibility of false triggering from noise that may be present on the voltages being monitored. When the filter is disabled, the comparator output will be delayed by 16µ ...
Page 20
... Lattice Semiconductor VMON Voltage Measurement with the On-chip Analog to Digital Converter (ADC) The ispPAC-POWR1220 has an on-chip analog to digital converter that can be used for measuring the voltages at the VMON inputs. The ADC is also used in closed loop trimming of DC-DC converters. Close loop trimming is cov- ered later in this document ...
Page 21
... GLB1, GLB2, and GLB3. Each GLB is made macrocells. In total, there are 48 macrocells in the ispPAC-POWR1220AT8 device. The output signals of the ispPAC-POWR1220AT8 device are derived from GLBs as shown in Figure 1-10. Additionally, the GLB3 generates the timer control and trimming block controls ...
Page 22
... Polarity Clock Clock and Timer Functions Figure 1-12 shows a block diagram of the ispPAC-POWR1220AT8’s internal clock and timer systems. The master clock operates at a fixed frequency of 8MHz, from which a fixed 250kHz PLD clock is derived. Figure 1-12. Clock and Timer System Internal ...
Page 23
... Lattice Semiconductor cuits, ADC and trim circuits. The ispPAC-POWR1220AT8 can be programmed to operate in three modes: Master mode, Standalone mode and Slave mode. Table 1-5 summarizes the operating modes of ispPAC-POWR1220AT8. Table 1-5. ispPAC-POWR1220AT8 Operating Modes Timer Operating Mode SW0 SW1 Standalone Closed Open ...
Page 24
... Controlling Power Supply Output Voltage by Margin/ Trim Block One of the key features of the ispPAC-POWR1220AT8 is its ability to make adjustments to the power supplies that it may also be monitoring and/or sequencing. This is accomplished through the Trim and Margin Block of the device ...
Page 25
... When the VPS[1:0] = 00, representing Voltage Profile 0: (Voltage Profile 0 is recommended to be used for the nor- mal circuit operation) The output voltage of the DC-DC converter controlled by the Trim 1 pin of the ispPAC-POWR1220AT8 will be 1V and that TrimCell is operating in closed loop trim mode. At the same time, the DC-DC converters controlled by Trim 2, Trim 3 and Trim 8 pins output 1 ...
Page 26
... Voltage Profile Control The Margin / Trim Block of ispPAC-POWR1220AT8 consists of eight TrimCells. Because all eight TrimCells in the Margin / Trim Block are controlled by two common voltage profile control signals, they all operate at the same volt- age profile. These common voltage profile control signals are derived from a Control Multiplexer. One set of voltage profile control inputs to the control multiplexer is from a pair of device pins: VPS0, VPS1 ...
Page 27
... Register 0 to DAC Register 3) are stored in the E stored in volatile registers. Two multiplexers (Mode Mux and Profile Mux) control the routing of the code to the DAC. The Profile Mux can be controlled by common TrimCell voltage profile control signals. ispPAC-POWR1220AT8 Data Sheet ispPAC-POWR1220AT8 Margin/Trim Block ...
Page 28
... Lattice Semiconductor Figure 1-18. ispPAC-POWR1220AT8 Output TrimCell VOLTAGE DAC REGISTER 3 PROFILE CMOS) VOLTAGE DAC REGISTER 2 PROFILE CMOS) VOLTAGE DAC REGISTER 1 PROFILE CMOS) DAC REGISTER CMOS) VOLTAGE DAC REGISTER 2 PROFILE CLOSED LOOP TRIM REGISTER FROM CLOSED LOOP TRIM CIRCUIT Figure 1-15 shows four power supply voltages next to each DC-DC converter. When the Profile MUX is set to Volt- age Profile 3, the DC supply controlled by Trim 1 will ...
Page 29
... This operation iterates until the setpoint and the DC-DC converter voltage are equal. Figure 1-19 shows the closed loop trim operation of a TrimCell. At regular intervals (as determined by the Update Rate Control register) the ispPAC-POWR1220AT8 device initiates the closed loop power supply voltage correction cycle through the following blocks: • ...
Page 30
... Figure 1-20. Offset Voltage is Added to DAC Output Voltage to Derive Trim Pad Voltage 8 From Trim Registers (-320mV to +320mV) Update Rate Update Control Value Interval 00 580 µ 18.5 ms DAC 7 bits + Sign Offset (0.6V,0.8V,1.0V,1.25V) E2CMOS 1-30 ispPAC-POWR1220AT8 Data Sheet 2 C (same address TRIMCELL X TRIMx Pad 2 CMOS ...
Page 31
... Each slave device on a given I C bus is assigned a unique address. The ispPAC-POWR1220AT8 implements the 7- bit addressing portion of the standard. Any 7-bit address can be assigned to the ispPAC-POWR1220AT8 device by programming through JTAG. When selecting a device address, one should note that several addresses are ...
Page 32
... The first frame contains the 7-bit device address with the R/W bit held High. In the second frame the ispPAC-POWR1220AT8 asserts data out on the bus in response to the SCL signal. Note that the acknowledge signal in the second frame is asserted by the master device and not the ispPAC-POWR1220AT8. ...
Page 33
... SDA START The ispPAC-POWR1220AT8 provides 26 registers that can be accessed through its I provide the user with the ability to monitor and control the device’s inputs and outputs, and transfer data to and from the device. Table provides a summary of these registers. 2 Table 1- Control Registers ...
Page 34
... VMON8A b7 b6 0x02 - VMON_STATUS2 (Read Only) VMON12B VMON12A also possible to directly read the value of the voltage present on any of the VMON inputs by using the ispPAC- POWR1220AT8’s ADC. Three registers provide the I Figure 1-25. ADC Interface Registers 0x07 - ADC_VALUE_LOW (Read Only 0x08 - ADC_VALUE_HIGH (Read Only) ...
Page 35
... DONE bit at clock rates lower CONVERT 2 C clock rate is less than 50kHz, the DONE bit may or may time period between subsequent ADC convert commands CONVERT 1-35 ispPAC-POWR1220AT8 Data Sheet Full-Scale Range 2.048 V 6.144 V SEL0 Input Channel 0 VMON1 ...
Page 36
... GP_OUTPUT registers. PLD Output/Input_Value Register Select (E 2 Configuration) 6 MUX USERJTAG 5 Bit 5 MUX 5 5 Input_Value Input_Status Interface Unit X IN6 IN5 IN4 bus instead of by the PLD array. The outputs 1-36 ispPAC-POWR1220AT8 Data Sheet PLD Array IN3 IN2 IN1 interface, as shown in Figure 1-27. The ...
Page 37
... X X OUT20 GP7 GP6 GP5_ENb GP4 GP15 GP14 GP13 GP12 GP20 interface, with the register mapping shown in Figure 1-28. 1-37 ispPAC-POWR1220AT8 Data Sheet 20 HVOUT[1..4] OUT[5..20] HVOUT3 HVOUT2 HVOUT1 OUT11 OUT10 OUT9 OUT19 OUT18 OUT17 GP3 GP2 GP1 GP11 GP10 GP9 GP19 ...
Page 38
... The I C interface also provides the ability to initiate reset operations. The ispPAC-POWR1220AT8 may be reset by issuing a write of any value to the I is equivalent to toggling the Resetb pin of the chip. Refer to the Resetb Signal, RESET Command via JTAG or I section of this data sheet for further information. ...
Page 39
... Lattice Semiconductor The ispPAC-POWR1220AT8 also provides the user with the ability to program the trim values over the I by writing the appropriate binary word to the associated trim register (Figure 1-30). 2 Figure 1-30 Trim Registers 0x13 - TRIM1_TRIM (Read/Write 0x14 - TRIM2_TRIM (Read/Write 0x15 - TRIM3_TRIM (Read/Write) ...
Page 40
... After OUT5/SMBA has been released, the bus master (typically a microcontroller) may opt to perform some service functions in which it may send data to or read data from the ispPAC-POWR1220AT8. As part of the service func- tions, the bus master will typically need to clear whatever condition initiated the SMBAlert request, and will also need to reset GP5_ENb to re-enable the SMBAlert function ...
Page 41
... Circuit designs are entered graphically and then verified, all within the PAC-Designer environ- ment. Full device programming is supported using PC parallel port I/O operations and a download cable connected to the serial programming interface pins of the ispPAC-POWR1220AT8. A library of configurations is included with basic solutions and examples of advanced circuit techniques are available on the Lattice web site for downloading. ...
Page 42
... TDI. When the internally pulled-up TDISEL = 1, standard TDI pin is enabled and when the TDISEL = 0, ATDI is enabled. In order to use this feature the JTAG signals of the ispPAC-POWR1220AT8 are connected to the header as shown in Figure 1-34. Note: The ispPAC-POWR1220AT8 should be the last device in the JTAG chain. ...
Page 43
... VCCA pins). In addition, to enable the on-chip JTAG interface circuitry, power should be applied to the VCCJ pin. When the ispPAC-POWR1220AT8 is powered by the VCCPROG pin, no power should be applied to the VCCD and VCCA pins. Additionally, other than JTAG I/O pins, all digital output pins are in Hi-Z state, HVOUT pins configured as MOSFET driver are driven low, and all other inputs are ignored ...
Page 44
... IEEE Standard 1149.1 Interface (JTAG) Serial Port Programming Interface Communication with the ispPAC-POWR1220AT8 is facilitated via an IEEE 1149.1 test access port (TAP used by the ispPAC-POWR1220AT8 as a serial programming interface. A brief description of the ispPAC-POWR1220AT8 JTAG interface follows. For complete details of the reference specifica- tion, refer to the publication, Standard Test Access Port and Boundary-Scan Architecture, IEEE Std 1149 ...
Page 45
... E CMOS cells these non-volatile cells that store the configuration or the ispPAC-POWR1220AT8. A set of instructions are defined that access all data registers and perform other internal control operations. For compatibil- ity between compliant devices, two data registers are mandated by the IEEE 1149.1 specification. Others are func- tionally specified, but inclusion is strictly optional ...
Page 46
... BYPASS and EXTEST instruction code patterns being specifically called out (all ones and all zeroes respec- tively). The ispPAC-POWR1220AT8 contains the required minimum instruction set as well as one from the optional instruction set. In addition, there are several proprietary instructions that allow the device to be configured and ver- ...
Page 47
... BYPASS is one of the three required instructions. It selects the Bypass Register to be connected between TDI and TDO and allows serial data to be transferred through the device without affecting the operation of the ispPAC- POWR1220AT8. The IEEE 1149.1 standard defines the bit code of this instruction to be all ones (11111111). ...
Page 48
... Lattice Semiconductor ispPAC-POWR1220AT8 has no boundary scan logic, the device is put in the BYPASS mode to ensure specification compatibility. The bit code of this instruction is defined by the 1149.1 standard to be all zeros (00000000). The optional IDCODE (identification code) instruction is incorporated in the ispPAC-POWR1220AT8 and leaves it in its functional mode when executed ...
Page 49
... Lattice Semiconductor DISCHARGE – This instruction is used to discharge the internal programming supply voltage after an erase or pro- gramming cycle and prepares ispPAC-POWR1220AT8 for a read cycle. This instruction also forces the outputs into the OUTPUTS_HIGHZ. CFG_ADDRESS – This instruction is used to set the address of the CFG array for subsequent program or read operations. This instruction also forces the outputs into the OUTPUTS_HIGHZ. CFG_DATA_SHIFT – ...
Page 50
... The device must already be in programming mode (PROGRAM_ENABLE instruction). This instruction also forces the outputs into the OUTPUTS_HIGHZ. ERASE_DONE_BIT – This instruction clears the 'Done' bit, which prevents the ispPAC-POWR1220AT8 sequence from starting. PROGRAM_DONE_BIT – This instruction sets the 'Done' bit, which enables the ispPAC-POWR1220AT8 sequence to start. RESET – ...
Page 51
... EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. 0.20 C A-B D 100X 0.20 H A-B SEE DETAIL 'A' C SEATING PLANE A LEAD FINISH 0.10 C DETAIL 'A' BASE METAL 1-51 ispPAC-POWR1220AT8 Data Sheet D1 D BOTTOM VIEW GAUGE PLANE H A2 0.20 MIN. 0 1.00 REF. SYMBOL MIN. NOM. MAX 1.60 A1 0.05 - 0.15 A2 1.35 1 ...
Page 52
... Device Family Device Number ispPAC-POWR1220AT8 Ordering Information Conventional Packaging Part Number ispPAC-POWR1220AT8-01T100I ispPAC-POWR1220AT8-02T100I Lead-Free Packaging Part Number ispPAC-POWR1220AT8-01TN100I ispPAC-POWR1220AT8-02TN100I ispPAC-POWR1220AT8 Data Sheet Operating Temperature Range I = Industrial (-40 Package T = 100-pin TQFP TN = Lead-Free 100-pin TQFP* Performance Grade 10V HVOUT 12V HVOUT Package ...
Page 53
... OUT13 17 OUT14 18 OUT15 19 OUT16 20 OUT17 21 GNDD 22 OUT18 23 OUT19 24 OUT20 25 Technical Support Assistance Hotline: 1-800-LATTICE (North America) +1-503-268-8001 (Outside North America) e-mail: isppacs@latticesemi.com Internet: www.latticesemi.com ispPAC-POWR1220AT8 Data Sheet ispPAC-POWR1220AT8 100-Pin TQFP 1-53 75 TRIM6 74 TRIM7 73 TRIM8 72 VMON12 71 VMON12GS 70 VMON11 69 VMON11GS 68 VMON10 67 VMON10GS 66 VMON9 65 ...
Page 54
... Modified PLD Architecture figure to show input registers. 2 Updated I C Control Registers table. VCCPROG pin usage clarification added. VCCPROG pin usage further clarified. Added product information for ispPAC-POWR1220AT8-02. T changed from a MIN to a MAX. GOOD ispPAC-POWR1220AT8 Alternate TDI Configuration Diagram clarified. 1-54 2 and V specifications for I C interface ...