LC4256V-75TN176C Lattice, LC4256V-75TN176C Datasheet - Page 29

• Manufacturer Part Number: LC4256V-75TN176C
• Description: CPLD - Complex Programmable Logic Devices 400MHZ 256 Macrocell 3.3 V 7.5 tPD
• Manufacturer: Lattice

Specifications of LC4256V-75TN176C

• Memory Type: EEPROM
• Number Of Macrocells: 256
• Number Of Product Terms Per Macro: 80
• Maximum Operating Frequency: 322 MHz
• Delay Time: 3 ns
• Number Of Programmable I/os: 44
• Operating Supply Voltage: 3.3 V
• Supply Current: 12.5 mA
• Maximum Operating Temperature: + 90 C
• Minimum Operating Temperature: 0 C
• Package / Case: TQFP-176
• Mounting Style: SMD/SMT
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
ispMACH 4000V/B/C Internal Timing Parameters
Parameter
In/Out Delays
t
t
t
t
t
t
Routing/GLB Delays
t
t
t
t
t
t
Register/Latch Delays
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Control Delays
t
t
t
t
IN
GOE
GCLK_IN
BUF
EN
DIS
ROUTE
MCELL
INREG
FBK
PDb
PDi
S
S_PT
ST
ST_PT
H
HT
SIR
SIR_PT
HIR
HIR_PT
COi
CES
CEH
SL
SL_PT
HL
GOi
PDLi
SRi
SRR
BCLK
PTCLK
BSR
PTSR
Input Buffer Delay
Global OE Pin Delay
Global Clock Input Buffer Delay
Delay through Output Buffer
Output Enable Time
Output Disable Time
Delay through GRP
Macrocell Delay
Input Buffer to Macrocell Register Delay
Internal Feedback Delay
5-PT Bypass Propagation Delay
Macrocell Propagation Delay
D-Register Setup Time (Global Clock)
D-Register Setup Time (Product Term Clock)
T-Register Setup Time (Global Clock)
T-Register Setup Time (Product Term Clock)
D-Register Hold Time
T-Register Hold Time
D-Input Register Setup Time (Global Clock)
D-Input Register Setup Time (Product Term Clock)
D-Input Register Hold Time (Global Clock)
D-Input Register Hold Time (Product Term Clock)
Register Clock to Output/Feedback MUX Time
Clock Enable Setup Time
Clock Enable Hold Time
Latch Setup Time (Global Clock)
Latch Setup Time (Product Term Clock)
Latch Hold Time
Latch Gate to Output/Feedback MUX Time
Propagation Delay through Transparent Latch to Output/
Feedback MUX
Asynchronous Reset or Set to Output/Feedback MUX
Delay
Asynchronous Reset or Set Recovery Time
GLB PT Clock Delay
Macrocell PT Clock Delay
GLB PT Set/Reset Delay
Macrocell PT Set/Reset Delay
Description
Over Recommended Operating Conditions
29
ispMACH 4000V/B/C/Z Family Data Sheet
Min.
1.32
1.32
1.52
1.32
1.68
1.68
1.52
1.45
0.68
0.68
2.25
1.88
1.32
1.32
1.17
0.28
1.67
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-5
Max.
0.95
4.04
1.83
1.00
0.96
0.96
1.51
1.05
0.56
0.00
1.54
0.94
0.52
0.33
0.25
1.12
0.87
1.83
2.51
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Min.
1.57
1.32
1.77
1.32
2.93
2.93
1.57
1.45
1.18
1.18
2.25
1.88
1.57
1.32
1.17
0.28
1.67
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-75
Max.
0.25
1.50
6.04
2.28
1.50
0.96
0.96
2.26
1.45
0.96
0.00
2.24
1.24
0.67
0.33
1.12
0.87
1.83
3.41
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Min.
1.57
1.32
1.77
1.32
3.93
3.93
1.57
1.45
1.18
1.18
2.25
1.88
1.57
1.32
1.17
0.28
1.67
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-10
Max.
2.00
7.04
3.28
1.50
0.96
0.96
3.26
1.95
1.46
0.00
3.24
1.74
1.17
0.33
0.25
0.62
0.87
1.83
3.41
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns