LC4256V-75TN176C Lattice, LC4256V-75TN176C Datasheet - Page 35

no-image

LC4256V-75TN176C

Manufacturer Part Number
LC4256V-75TN176C
Description
CPLD - Complex Programmable Logic Devices 400MHZ 256 Macrocell 3.3 V 7.5 tPD
Manufacturer
Lattice
Datasheet

Specifications of LC4256V-75TN176C

Memory Type
EEPROM
Number Of Macrocells
256
Number Of Product Terms Per Macro
80
Maximum Operating Frequency
322 MHz
Delay Time
3 ns
Number Of Programmable I/os
44
Operating Supply Voltage
3.3 V
Supply Current
12.5 mA
Maximum Operating Temperature
+ 90 C
Minimum Operating Temperature
0 C
Package / Case
TQFP-176
Mounting Style
SMD/SMT
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LC4256V-75TN176C
Manufacturer:
SIMCOM
Quantity:
1 000
Part Number:
LC4256V-75TN176C
Manufacturer:
Lattice
Quantity:
218
Part Number:
LC4256V-75TN176C
Manufacturer:
LATTICE22
Quantity:
207
Part Number:
LC4256V-75TN176C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Part Number:
LC4256V-75TN176C
Manufacturer:
Lattice
Quantity:
1 000
Part Number:
LC4256V-75TN176C
Manufacturer:
LATTICE
Quantity:
20 000
ispMACH 4000V/B/C Timing Adders
Lattice Semiconductor
Optional Delay Adders
t
t
t
t
t
LVTTL_in
LVCMOS33_in
LVCMOS25_in
LVCMOS18_in
PCI_in
t
LVTTL_out
LVCMOS33_out t
LVCMOS25_out t
LVCMOS18_out t
PCI_out
Slow Slew
Note: Open drain timing is the same as corresponding LVCMOS timing.
1. Refer to Technical Note TN1004: ispMACH 4000 Timing Model Design and Usage Guidelines for information regarding use of these adders.
INDIO
EXP
ORP
BLA
IOI
IOO
Input Adjusters
Output Adjusters
Adder
Type
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
INREG
MCELL
ROUTE
IN
GOE
IN
GOE
IN
GOE
IN
GOE
IN
GOE
BUF
BUF
BUF
BUF
BUF
BUF
Parameter
, t
, t
, t
, t
, t
, t
, t
, t
, t
, t
, t
GCLK_IN
GCLK_IN
GCLK_IN
GCLK_IN
GCLK_IN
Base
EN
EN
EN
EN
EN
EN
, t
, t
, t
, t
, t
DIS
DIS
DIS
DIS
DIS
,
,
,
,
,
Input register delay
Product term expander
delay
Output routing pool delay
Additional block loading
adder
Using LVTTL standard
Using LVCMOS 3.3
standard
Using LVCMOS 2.5
standard
Using LVCMOS 1.8
standard
Using PCI compatible
input
Output configured as
TTL buffer
Output configured as
3.3V buffer
Output configured as
2.5V buffer
Output configured as
1.8V buffer
Output configured as
PCI compatible buffer
Output configured for
slow slew rate
Description
1
Min.
35
-25
Max.
ispMACH 4000V/B/C/Z Family Data Sheet
0.95
0.33
0.05
0.03
0.60
0.60
0.60
0.00
0.60
0.20
0.20
0.10
0.00
0.20
1.00
Min.
-27
Max.
1.00
0.33
0.05
0.05
0.60
0.60
0.60
0.00
0.60
0.20
0.20
0.10
0.00
0.20
1.00
Min.
-3
Max.
1.00
0.33
0.05
0.05
0.60
0.60
0.60
0.00
0.60
0.20
0.20
0.10
0.00
0.20
1.00
Min.
-35
Max.
0.33
0.05
0.60
0.60
0.00
0.60
0.20
0.20
0.10
0.00
0.20
1.00
1.00
0.05
0.60
Timing v.3.2
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

Related parts for LC4256V-75TN176C