LCMXO1200C-3FTN256C Lattice, LCMXO1200C-3FTN256C Datasheet - Page 17

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LCMXO1200C-3FTN256C

Manufacturer Part Number
LCMXO1200C-3FTN256C
Description
CPLD - Complex Programmable Logic Devices 1200 LUTS 211 I/O
Manufacturer
Lattice
Series
MachXOr
Datasheet

Specifications of LCMXO1200C-3FTN256C

Memory Type
SRAM
Number Of Macrocells
600
Delay Time
5.1 ns
Number Of Programmable I/os
211
Operating Supply Voltage
1.8 V, 2.5 V, 3.3 V
Supply Current
21 mA
Maximum Operating Temperature
+ 90 C
Minimum Operating Temperature
0 C
Package / Case
ftBGA-256
Mounting Style
SMD/SMT
Supply Voltage (max)
3.465 V
Supply Voltage (min)
1.71 V
Cpld Type
FLASH
No. Of Macrocells
1200
No. Of I/o's
211
Propagation Delay
5.1ns
Global Clock Setup Time
1.6ns
Frequency
420MHz
Supply Voltage Range
1.71V To 3.465V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LCMXO1200C-3FTN256C
Manufacturer:
Lattice
Quantity:
135
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LCMXO1200C-3FTN256C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Part Number:
LCMXO1200C-3FTN256C
Manufacturer:
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Quantity:
20 000
Part Number:
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Manufacturer:
LATTICE
Quantity:
12 052
Part Number:
LCMXO1200C-3FTN256C
Manufacturer:
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Quantity:
11 264
Lattice Semiconductor
PIO Groups
On the MachXO devices, PIO cells are assembled into two different types of PIO groups, those with four PIO cells
and those with six PIO cells. PIO groups with four IOs are placed on the left and right sides of the device while PIO
groups with six IOs are placed on the top and bottom. The individual PIO cells are connected to their respective
sysIO buffers and PADs.
On all MachXO devices, two adjacent PIOs can be joined to provide a complementary Output driver pair. The I/O
pin pairs are labeled as "T" and "C" to distinguish between the true and complement pins.
The MachXO1200 and MachXO2280 devices contain enhanced I/O capability. All PIO pairs on these larger
devices can implement differential receivers. In addition, half of the PIO pairs on the left and right sides of these
devices can be configured as LVDS transmit/receive pairs. PIOs on the top of these larger devices also provide PCI
support.
Figure 2-15. Group of Four Programmable I/O Cells
Figure 2-16. Group of Six Programmable I/O Cells
PIO
The PIO blocks provide the interface between the sysIO buffers and the internal PFU array blocks. These blocks
receive output data from the PFU array and a fast output data signal from adjacent PFUs. The output data and fast
Four PIOs
Six PIOs
This structure is used on the top
and bottom of MachXO devices
This structure is used on the
left and right of MachXO devices
2-14
PIO A
PIO B
PIO C
PIO D
PIO E
PIO F
PIO B
PIO A
PIO C
PIO D
PADB "C"
PADA "T"
PADC "T"
PADE "T"
PADF "C"
PADD "C"
PADB "C"
PADA "T"
PADC "T"
PADD "C"
MachXO Family Data Sheet
Architecture

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