LCMXO256C-3TN100C Lattice, LCMXO256C-3TN100C Datasheet - Page 25

• Manufacturer Part Number: LCMXO256C-3TN100C
• Description: CPLD - Complex Programmable Logic Devices 256 LUTS 78 I/O
• Manufacturer: Lattice
• Series: MachXOr

Specifications of LCMXO256C-3TN100C

• Memory Type: SRAM
• Number Of Macrocells: 128
• Delay Time: 4.9 ns
• Number Of Programmable I/os: 78
• Operating Supply Voltage: 1.8 V, 2.5 V, 3.3 V
• Supply Current: 13 mA
• Maximum Operating Temperature: + 90 C
• Minimum Operating Temperature: 0 C
• Package / Case: TQFP-100
• Mounting Style: SMD/SMT
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 1.71 V
• Cpld Type: FLASH
• No. Of Macrocells: 256
• No. Of I/o's: 78
• Propagation Delay: 4.9ns
• Global Clock Setup Time: 1.8ns
• Frequency: 420MHz
• Supply Voltage Range: 1.71V To 3.465V
• Rohs Compliant: Yes
• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 4.9ns
• Voltage Supply - Internal: 1.71 V ~ 3.465 V
• Number Of Logic Elements/blocks: -
• Number Of Gates: -
• Number Of I /o: 78
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Device Configuration
All MachXO devices contain a test access port that can be used for device configuration and programming.
The non-volatile memory in the MachXO can be configured in two different modes:
The SRAM configuration memory can be configured in three different ways:
Figure 2-22 provides a pictorial representation of the different programming modes available in the MachXO
devices. On power-up, the SRAM is ready to be configured with IEEE 1149.1 serial TAP port using IEEE 1532 pro-
tocols.
Leave Alone I/O
When using IEEE 1532 mode for non-volatile memory programming, SRAM configuration, or issuing a refresh
command, users may specify I/Os as high, low, tristated or held at current value. This provides excellent flexibility
for implementing systems where reconfiguration or reprogramming occurs on-the-fly.
TransFR (Transparent Field Reconfiguration)
TransFR (TFR) is a unique Lattice technology that allows users to update their logic in the field without interrupting
system operation using a single ispVM command. See Lattice technical note #TN1087, Minimizing System Inter-
ruption During Configuration Using TransFR Technology, for details.
Security
The MachXO devices contain security bits that, when set, prevent the readback of the SRAM configuration and
non-volatile memory spaces. Once set, the only way to clear the security bits is to erase the memory space.
For more information on device configuration, please see details of additional technical documentation at the end
of this data sheet.
• In IEEE 1532 mode via the IEEE 1149.1 port. In this mode, the device is off-line and I/Os are controlled by
• In background mode via the IEEE 1149.1 port. This allows the device to remain operational in user mode
• At power-up via the on-chip non-volatile memory.
• After a refresh command is issued via the IEEE 1149.1 port.
• In IEEE 1532 mode via the IEEE 1149.1 port.
BSCAN registers.
while reprogramming takes place.
2-22
MachXO Family Data Sheet
Architecture