LC4256V-75TN144C Lattice, LC4256V-75TN144C Datasheet - Page 22

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LC4256V-75TN144C

Manufacturer Part Number
LC4256V-75TN144C
Description
CPLD - Complex Programmable Logic Devices 400MHZ 256 Macrocell 3.3 V 7.5 tPD
Manufacturer
Lattice
Datasheet

Specifications of LC4256V-75TN144C

Memory Type
EEPROM
Number Of Macrocells
256
Number Of Product Terms Per Macro
80
Maximum Operating Frequency
322 MHz
Delay Time
3 ns
Number Of Programmable I/os
48
Operating Supply Voltage
3.3 V
Supply Current
12.5 mA
Maximum Operating Temperature
+ 90 C
Minimum Operating Temperature
0 C
Package / Case
TQFP-144
Mounting Style
SMD/SMT
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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0
Lattice Semiconductor
ispMACH 4000V/B/C External Switching Characteristics
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
f
1. Timing numbers are based on default LVCMOS 1.8 I/O buffers. Use timing adjusters provided to calculate other standards.
2. Measured using standard switching circuit, assuming GRP loading of 1 and 1 output switching.
3. Pulse widths and clock widths less than minimum will cause unknown behavior.
4. Standard 16-bit counter using GRP feedback.
Parameter
PD
PD_MC
S
ST
SIR
SIRZ
H
HT
HIR
HIRZ
CO
R
RW
PTOE/DIS
GPTOE/DIS
GOE/DIS
CW
GW
WIR
MAX
MAX
4
(Ext.)
5-PT bypass combinatorial propagation
delay
20-PT combinatorial propagation delay
through macrocell
GLB register setup time before clock
GLB register setup time before clock
with T-type register
GLB register setup time before clock,
input register path
GLB register setup time before clock
with zero hold
GLB register hold time after clock
GLB register hold time after clock with
T-type register
GLB register hold time after clock, input
register path
GLB register hold time after clock, input
register path with zero hold
GLB register clock-to-output delay
External reset pin to output delay
External reset pulse duration
Input to output local product term output
enable/disable
Input to output global product term
output enable/disable
Global OE input to output enable/disable
Global clock width, high or low
Global gate width low (for low
transparent) or high (for high transparent)
Input register clock width, high or low
Clock frequency with internal feedback
Clock frequency with external feedback,
[1/ (t
S
+ t
CO
)]
Description
1, 2, 3
Over Recommended Operating Conditions
Min.
400
250
1.8
2.0
0.7
1.7
0.0
0.0
0.9
0.0
1.5
1.1
1.1
1.1
-25
22
Max.
2.5
3.2
4.0
5.0
2.2
3.5
3.0
ispMACH 4000V/B/C/Z Family Data Sheet
Min.
333
222
1.8
2.0
1.0
2.0
0.0
0.0
1.0
0.0
1.5
1.3
1.3
1.3
-27
Max.
2.7
3.5
2.7
4.0
4.5
6.5
3.5
Min.
322
212
2.0
2.2
1.0
2.0
0.0
0.0
1.0
0.0
1.5
1.3
1.3
1.3
-3
Max.
3.0
3.8
2.7
4.4
5.0
8.0
4.0
Min.
322
212
2.0
2.2
1.0
2.0
0.0
0.0
1.0
0.0
1.5
1.3
1.3
1.3
-35
Max.
3.5
4.2
2.7
4.5
5.5
8.0
4.5
-
Timing v.3.2
Units
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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