LC4256V-75TN144C Lattice, LC4256V-75TN144C Datasheet - Page 7

no-image

LC4256V-75TN144C

Manufacturer Part Number
LC4256V-75TN144C
Description
CPLD - Complex Programmable Logic Devices 400MHZ 256 Macrocell 3.3 V 7.5 tPD
Manufacturer
Lattice
Datasheet

Specifications of LC4256V-75TN144C

Memory Type
EEPROM
Number Of Macrocells
256
Number Of Product Terms Per Macro
80
Maximum Operating Frequency
322 MHz
Delay Time
3 ns
Number Of Programmable I/os
48
Operating Supply Voltage
3.3 V
Supply Current
12.5 mA
Maximum Operating Temperature
+ 90 C
Minimum Operating Temperature
0 C
Package / Case
TQFP-144
Mounting Style
SMD/SMT
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LC4256V-75TN144C
Manufacturer:
Lattice
Quantity:
141
Part Number:
LC4256V-75TN144C
Manufacturer:
LATTICE
Quantity:
1 831
Part Number:
LC4256V-75TN144C
Manufacturer:
LATTICE23
Quantity:
50
Part Number:
LC4256V-75TN144C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Part Number:
LC4256V-75TN144C
Manufacturer:
LATTICE
Quantity:
1 500
Part Number:
LC4256V-75TN144C
Manufacturer:
LATTICE
Quantity:
20 000
Part Number:
LC4256V-75TN144C
Manufacturer:
LATTICE
Quantity:
13 769
Part Number:
LC4256V-75TN144C
0
Lattice Semiconductor
Table 5. Product Term Expansion Capability
Every time the super cluster allocator is used, there is an incremental delay of t
tor is used, all destinations other than the one being steered to, are given the value of ground (i.e., if the super clus-
ter is steered to M (n+4), then M (n) is ground).
Macrocell
The 16 macrocells in the GLB are driven by the 16 outputs from the logic allocator. Each macrocell contains a pro-
grammable XOR gate, a programmable register/latch, along with routing for the logic and control functions.
Figure 5 shows a graphical representation of the macrocell. The macrocells feed the ORP and GRP. A direct input
from the I/O cell allows designers to use the macrocell to construct high-speed input registers. A programmable
delay in this path allows designers to choose between the fastest possible set-up time and zero hold time.
Figure 5. Macrocell
Enhanced Clock Multiplexer
The clock input to the flip-flop can select any of the four block clocks along with the shared PT clock, and true and
complement forms of the optional individual term clock. An 8:1 multiplexer structure is used to select the clock. The
eight sources for the clock multiplexer are as follows:
• Block CLK0
• Block CLK1
Single PT
Expansion
Chain-0
Chain-1
Chain-2
Chain-3
Chains
PT Initialization/CE (optional)
PT Initialization (optional)
Shared PT Initialization
From Logic Allocator
PT Clock (optional)
Shared PT Clock
Block CLK0
Block CLK1
Block CLK2
Block CLK3
Macrocells Associated with Expansion Chain
M2 → M6 → M10 → M14 → M2
M3 → M7 → M11 → M15 → M3
M0 → M4 → M8 → M12 → M0
M1 → M5 → M9 → M13 → M1
(with Wrap Around)
Initialization
Power-up
7
ispMACH 4000V/B/C/Z Family Data Sheet
Delay
D/T/L
CE
R
EXP
P
Q
. When the super cluster alloca-
Macrocell
Max PT/
From I/O Cell
To ORP
To GRP
75
80
75
70

Related parts for LC4256V-75TN144C