A3PN030-ZVQG100 Actel, A3PN030-ZVQG100 Datasheet - Page 33

FPGA - Field Programmable Gate Array 30K System Gates ProASIC3 nano

A3PN030-ZVQG100

Manufacturer Part Number
A3PN030-ZVQG100
Description
FPGA - Field Programmable Gate Array 30K System Gates ProASIC3 nano
Manufacturer
Actel
Datasheet

Specifications of A3PN030-ZVQG100

Processor Series
A3PN030
Core
IP Core
Number Of Macrocells
256
Maximum Operating Frequency
350 MHz
Number Of Programmable I/os
77
Supply Voltage (max)
3.3 V
Supply Current
2 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
- 20 C
Development Tools By Supplier
AGLN-Nano-Kit, AGLN-Z-Nano-Kit, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FloasPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.5 V
Number Of Gates
30 K
Package / Case
VQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
A3PN030-ZVQG100
Manufacturer:
ACTEL
Quantity:
1 213
Part Number:
A3PN030-ZVQG100
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
A3PN030-ZVQG100I
Manufacturer:
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Part Number:
A3PN030-ZVQG100I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Detailed I/O DC Characteristics
Table 2-20 • Input Capacitance
Table 2-21 • I/O Output Buffer Maximum Resistances
Table 2-22 • I/O Weak Pull-Up/Pull-Down Resistances
Symbol
C
C
Standard
3.3 V LVTTL / 3.3 V LVCMOS
3.3 V LVCMOS Wide Range
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
Notes:
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance
2. R
3. R
VCCI
3.3 V
3.3 V (wide range I/Os)
2.5 V
1.8 V
1.5 V
Notes:
1. R
2. R
IN
INCLK
values depend on V
considerations and detailed output buffer resistances, use the corresponding IBIS models located on the
Actel website at http://www.actel.com/download/ibis/default.aspx.
(PULL-DOWN-MAX)
(PULL-UP-MAX)
(WEAK PULL-UP-MAX)
(WEAK PULLDOWN-MAX)
Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values
Input capacitance
Input capacitance on the clock pin
= (VCCImax – VOHspec) / I
= (VOLspec) / IOLspec
= (VCCImax – VOHspec) / I
CCI
= (VOLspec) / I
Definition
, drive strength selection, temperature, and process. For board design
10 K
10 K
18 K
19 K
Min.
11 K
R
(WEAK PULL-UP)
(WEAK PULLDOWN-MIN)
R e v i s i o n 8
(Ω)
O H spec
Drive Strength
(WEAK PULL-UP-MIN)
100 µA
2 mA
4 mA
6 mA
8 mA
2 mA
4 mA
6 mA
8 mA
2 mA
4 mA
2 mA
Max.
45 K
45 K
55 K
70 K
90 K
1
1
VIN = 0, f = 1.0 MHz
VIN = 0, f = 1.0 MHz
Conditions
10 K
10 K
12 K
17 K
19 K
Min.
R
R
(WEAK PULL-DOWN)
PULL-DOWN
software default drive
ProASIC3 nano Flash FPGAs
Same as equivalent
(Ω)
100
100
100
100
200
100
200
50
50
50
50
Min.
2
(Ω)
Max.
140 K
8
8
110 K
Max.
R
45 K
45 K
74 K
PULL-UP
2
(Ω)
300
300
150
150
200
200
100
100
225
224
112
Units
3
pF
pF
2- 19

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