A3PN250-ZVQG100 Actel, A3PN250-ZVQG100 Datasheet - Page 66

FPGA - Field Programmable Gate Array 250K System Gates ProASIC3 nano

A3PN250-ZVQG100

Manufacturer Part Number
A3PN250-ZVQG100
Description
FPGA - Field Programmable Gate Array 250K System Gates ProASIC3 nano
Manufacturer
Actel
Datasheet

Specifications of A3PN250-ZVQG100

Processor Series
A3PN250
Core
IP Core
Number Of Macrocells
2048
Maximum Operating Frequency
350 MHz
Number Of Programmable I/os
68
Data Ram Size
36 Kbit
Delay Time
1.05 ns
Supply Voltage (max)
3.3 V
Supply Current
3 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
- 20 C
Development Tools By Supplier
AGLN-Nano-Kit, AGLN-Z-Nano-Kit, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FloasPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.5 V
Number Of Gates
250 K
Package / Case
VQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Manufacturer
Quantity
Price
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ACT
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Manufacturer:
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Part Number:
A3PN250-ZVQG100I
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ProASIC3 nano DC and Switching Characteristics
Figure 2-22 • Timing Model and Waveforms
Table 2-66 • Register Delays
2- 52
CLK
Data
EN
Out
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
PRE
CLR
CLKQ
SUD
HD
SUE
HE
CLR2Q
PRE2Q
REMCLR
RECCLR
REMPRE
RECPRE
WCLR
WPRE
CKMPWH
CKMPWL
For specific junction temperature and voltage supply levels, refer to
Commercial-Case Conditions: T
Timing Characteristics
Clock-to-Q of the Core Register
Data Setup Time for the Core Register
Data Hold Time for the Core Register
Enable Setup Time for the Core Register
Enable Hold Time for the Core Register
Asynchronous Clear-to-Q of the Core Register
Asynchronous Preset-to-Q of the Core Register
Asynchronous Clear Removal Time for the Core Register
Asynchronous Clear Recovery Time for the Core Register
Asynchronous Preset Removal Time for the Core Register
Asynchronous Preset Recovery Time for the Core Register
Asynchronous Clear Minimum Pulse Width for the Core Register
Asynchronous Preset Minimum Pulse Width for the Core Register
Clock Minimum Pulse Width HIGH for the Core Register
Clock Minimum Pulse Width LOW for the Core Register
50%
50%
t
SUE
t
HE
50%
t
CLKQ
50%
t
SUD
0
t
HD
t
PRE2Q
50%
50%
J
Description
= 70°C, Worst-Case VCC = 1.425 V
50%
t
WPRE
50%
50%
50%
t
t
RECPRE
WCLR
R e visio n 8
50%
t
50%
50%
CLR2Q
50%
t
RECCLR
Table 2-6 on page 2-5
50%
t
CKMPWH
0.55 0.63 0.74
0.43 0.49 0.57
0.00 0.00 0.00
0.45 0.52 0.61
0.00 0.00 0.00
0.40 0.45 0.53
0.40 0.45 0.53
0.00 0.00 0.00
0.22 0.25 0.30
0.00 0.00 0.00
0.22 0.25 0.30
0.22 0.25 0.30
0.22 0.25 0.30
0.36 0.41 0.48
0.32 0.37 0.43
t
50%
–2
REMPRE
for derating values.
t
CKMPWL
50%
–1
Std. Units
50%
50%
t
REMCLR
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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