FPGA - Field Programmable Gate Array 8K LUTs 201 I/O Inst on DSP 1.2V -5 Spd

 

LFXP2-8E-5FTN256I

Manufacturer Part NumberLFXP2-8E-5FTN256I
DescriptionFPGA - Field Programmable Gate Array 8K LUTs 201 I/O Inst on DSP 1.2V -5 Spd
ManufacturerLattice
LFXP2-8E-5FTN256I datasheets

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Specifications of LFXP2-8E-5FTN256I

Number Of Macrocells8000Number Of Programmable I/os201
Data Ram Size226304Supply Voltage (max)1.26 V
Maximum Operating Temperature+ 100 CMinimum Operating Temperature- 40 C
Mounting StyleSMD/SMTSupply Voltage (min)1.14 V
Package / CaseFTBGA-256Number Of Logic Elements/cells*
Number Of Labs/clbs*Total Ram Bits226304
Number Of I /o201Number Of Gates-
Voltage - Supply1.14 V ~ 1.26 VMounting Type*
Operating Temperature-40°C ~ 100°CPackage256FTBGA
Family NameLatticeXP2Device Logic Units8000
Typical Operating Supply Voltage1.2 VMaximum Number Of User I/os201
Ram Bits226304Re-programmability SupportYes
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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Lattice Semiconductor
Table 9-7. User Parameters in the IPexpress GUI (Continued)
User Parameters
Bypass
Desired Frequency User enters desired CLKOP frequency
Divider
CLKOP
Tolerance
Actual Frequency
Rising
Falling
Delay Multiplier
Enable
Bypass
CLKOS
Phase Shift
Rising
Delay Multiplier
Enable
Bypass
Frequency
CLKOK
Divider
Tolerance
Actual Frequency
CLKOK2
Enable
Provide PLL Reset
Provide CLKOK Divide Reset
Provide CLKOS Fine Delay Port
Import LPC to ispLEVER Project
PLL Modes of Operation
PLLs have many uses within a logic design. The two most popular are Clock Injection Removal and Clock Phase
Adjustment. These two modes of operation are described below.
PLL Clock Injection Removal
In this mode the PLL is used to reduce clock injection delay. Clock injection delay is the delay from the input pin of
the device to a destination element such as a flip-flop. The phase detector of the PLL aligns the CLKI with CLKFB.
If the CLKFB signal comes from the clock tree (CLKOP), then the PLL delay and the clock tree delay is removed.
Figure 9-10 Illustrates an example block diagram and waveform.
Description
Bypass PLL: CLKOP = CLKI
CLKOP Divider Setting (Divider Mode)
CLKOP tolerance users can tolerate
Actual frequency achievable. Read only
Rising Edge Trim
Falling Edge Trim
Number of delay steps
Enable CLKOS output clock
Bypass PLL: CLKOS = CLKI
CLKOS Static Phase Shift
Rising Edge Trim
Number of Delay steps
Enable CLKOS output clock
Bypass PLL: CLKOK = CLKI
User enters desired CLKOK frequency
CLKOK Divider Setting
CLKOK tolerance users can tolerate
Actual frequency achievable. Read only
Enable CLKOK2 output clock
Provide PLL Reset Port (RESET)
Provide CLKOK Reset Port (RSTK)
Provide CLKOS Fine Delay Port (WRDEL)
Import .lpc file to ispLEVER project
9-13
LatticeXP2 sysCLOCK PLL
Design and Usage Guide
Range
Default
ON/OFF
OFF
10 MHz to
100 MHz
435 MHz
2, 4, 8, 16, 32,
8
48, 64, 80
0.0, 0.1, 0.2, 0.5,
0.0
0.1, 0.2, 0.5, 1.0
—
—
ON/OFF
OFF
ON/OFF
OFF
0 to 7
0
ON/OFF
OFF
ON/OFF
OFF
0°, 22.5°,
0°
45°..337.5°
ON/OFF
OFF
0 to 7
0
ON/OFF
OFF
ON/OFF
OFF
78.125 kHz to
50 MHz
217.5 MHz
2 to 128
2
0.0, 0.1, 0.2, 0.5,
0.00
0.1, 0.2, 0.5, 1.0
—
—
ON/OFF
OFF
ON/OFF
OFF
ON/OFF
OFF
ON/OFF
OFF
ON/OFF
OFF

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