LFXP2-8E-5FTN256I | |
|---|---|
| Manufacturer Part Number | LFXP2-8E-5FTN256I |
| Description | FPGA - Field Programmable Gate Array 8K LUTs 201 I/O Inst on DSP 1.2V -5 Spd |
| Manufacturer | Lattice |
| LFXP2-8E-5FTN256I datasheets |
|
Availability: By request
International delivery:
Warranty: 60 days
×
- We provide standard 60-days warranty for all parts. If warranty differs we always mention it beforehand. In case of return we cover shipping costs.
- If you still have any questions - please contact us
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Shipping terms
- Standard delivery time differs from 5-8 business days if the supplier is a local one to 12-14 days if the suplier is from overseas. If delivery time differs it's always mentioned in our quotation.
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Specifications of LFXP2-8E-5FTN256I | |||
|---|---|---|---|
| Number Of Macrocells | 8000 | Number Of Programmable I/os | 201 |
| Data Ram Size | 226304 | Supply Voltage (max) | 1.26 V |
| Maximum Operating Temperature | + 100 C | Minimum Operating Temperature | - 40 C |
| Mounting Style | SMD/SMT | Supply Voltage (min) | 1.14 V |
| Package / Case | FTBGA-256 | Number Of Logic Elements/cells | * |
| Number Of Labs/clbs | * | Total Ram Bits | 226304 |
| Number Of I /o | 201 | Number Of Gates | - |
| Voltage - Supply | 1.14 V ~ 1.26 V | Mounting Type | * |
| Operating Temperature | -40°C ~ 100°C | Package | 256FTBGA |
| Family Name | LatticeXP2 | Device Logic Units | 8000 |
| Typical Operating Supply Voltage | 1.2 V | Maximum Number Of User I/os | 201 |
| Ram Bits | 226304 | Re-programmability Support | Yes |
| Lead Free Status / RoHS Status | Lead free / RoHS Compliant | ||
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PrevNext
Lattice Semiconductor
Table 9-11. DCS Modes of Operation
Attribute Name
Rising edge triggered, latched state is high
Falling edge triggered, latched state is low
Sel is active high, Disabled output is low
Sel is active high, Disabled output is high
DCS MODE
Sel is active low, Disabled output is low
Sel is active low, Disabled output is high
Buffer for CLK0
Buffer for CLK1
DCS Timing Diagrams
Each mode performs a unique operation. The clock output timing is determined by input clocks and the edge of the
SEL signal. Figure 9-19 describes the timing of each mode.
Figure 9-19. Timing Diagrams by DCS MODE
CLK0
CLK1
SEL
DCSOUT
SEL Falling edge:
- Wait for CLK1 rising edge,
latch output & remain high
- Switch output at CLK0 rising edge
CLK0
CLK1
SEL
DCSOUT
SEL Falling edge:
- Wait for CLK1 falling edge,
latch output & remain low
- Switch output at CLK0 falling edge
Description
DCS MODE = POS
DCS MODE = NEG
9-20
LatticeXP2 sysCLOCK PLL
Design and Usage Guide
Output
SEL=0
SEL=1
CLK0
CLK1
CLK0
CLK1
0
CLK1
HIGH_LOW
1
CLK1
HIGH_HIGH
CLK0
0
CLK0
1
LOW_HIGH
CLK0
CLK0
CLK1
CLK1
SEL Rising edge:
- Wait for CLK0 rising edge,
latch output & remain high
- Switch output at CLK1 rising edge
SEL Rising edge:
- Wait for CLK0 falling edge,
latch output & remain low
- Switch output at CLK1 falling edge
Value
POS
NEG
LOW_LOW
CLK0
CLK1
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