LFXP2-8E-5FTN256I | |
|---|---|
| Manufacturer Part Number | LFXP2-8E-5FTN256I |
| Description | FPGA - Field Programmable Gate Array 8K LUTs 201 I/O Inst on DSP 1.2V -5 Spd |
| Manufacturer | Lattice |
| LFXP2-8E-5FTN256I datasheets |
|
Availability: By request
International delivery:
Warranty: 60 days
×
- We provide standard 60-days warranty for all parts. If warranty differs we always mention it beforehand. In case of return we cover shipping costs.
- If you still have any questions - please contact us
×
Shipping terms
- Standard delivery time differs from 5-8 business days if the supplier is a local one to 12-14 days if the suplier is from overseas. If delivery time differs it's always mentioned in our quotation.
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Payment terms
- For new client payment term is payment in advance. At this moment we accept 3 payment methods: wire transfer, PayPal and Western Union. Credit card payment is under constrution and will be introduced soon. Escrow service is acceptable. Net terms for regular customers is not a problem. Working with us is totally safe for you.
- If you still have any questions - please contact us
Specifications of LFXP2-8E-5FTN256I | |||
|---|---|---|---|
| Number Of Macrocells | 8000 | Number Of Programmable I/os | 201 |
| Data Ram Size | 226304 | Supply Voltage (max) | 1.26 V |
| Maximum Operating Temperature | + 100 C | Minimum Operating Temperature | - 40 C |
| Mounting Style | SMD/SMT | Supply Voltage (min) | 1.14 V |
| Package / Case | FTBGA-256 | Number Of Logic Elements/cells | * |
| Number Of Labs/clbs | * | Total Ram Bits | 226304 |
| Number Of I /o | 201 | Number Of Gates | - |
| Voltage - Supply | 1.14 V ~ 1.26 V | Mounting Type | * |
| Operating Temperature | -40°C ~ 100°C | Package | 256FTBGA |
| Family Name | LatticeXP2 | Device Logic Units | 8000 |
| Typical Operating Supply Voltage | 1.2 V | Maximum Number Of User I/os | 201 |
| Ram Bits | 226304 | Re-programmability Support | Yes |
| Lead Free Status / RoHS Status | Lead free / RoHS Compliant | ||
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PrevNext
Lattice Semiconductor
General Description
The LatticeXP2 family of devices is designed with instant-on, standalone TAG memory that is always available.
TAG memory is organized as a one-page Flash non-volatile memory accessible by the hardwired Serial Peripheral
Interface port or the JTAG port.
The standalone TAG memory is ideal for use as scratch pad memory for critical data, board serialization, board
revision logs and programmed pattern identification.
The integration of TAG memory into the LatticeXP2 device family saves chip count and board space. It also can be
used to replace obsoleted low-density SPI EEPROM devices.
The hardwired SPI interface does not require the device to pre-program the configuration Flash first to enable the
SPI interface. The interface is already enabled when the device is shipped from Lattice, saving board test time.
The hard-wired SPI interface allows the TAG memory to retain its independent identity or accessible always in spite
of the TAG Memory Flash is embedded into the LatticeXP2 devices.
The hard-wired SPI interface is also important for field upgrades so that critical data can be maintained on the TAG
memory and guaranteed to be accessible even if the device is field upgraded to a new pattern.
The instant-on capability is achieved by enabling the SPI interface when the devices are shipped from Lattice.
Unlike the configuration Flash, the security setting of the device, standard or advanced, has no effect on the acces-
sibility of the TAG memory. Therefore, the TAG memory is always accessible.
The TAG memory, same as other Flash fuses, can also be programmed using the IEEE 1532 compliant program-
ming flow on the JTAG port for production programming support or for system debugging.
Pin Descriptions
The pins described below are not dedicated pins. If the TAG memory feature is not required, these pins can be reg-
ular user I/O pins. If the TAG memory feature is required, the TAG memory can be accessed by the internal SPI
interface through the core. The internal SPI interface makes the TAG Memory capable of supporting advanced
applications. For example:
2
1. Use an I
C to SPI translator to convert the SPI TAG memory to be an I
2. Route the four SPI interfaces to the other four user I/Os.
Selections are made using the ispLEVER design tool. By default, the external SPI interface is enabled and TAG
memory is selected.
The functional descriptions of the pins below are applicable to both the internal and external SPI interfaces.
Serial Data Input (SI)
The SPI Serial Data Input pin provides a means for commands and data to be serially written to (shifted into) the
device. Data is latched on the falling edge of the serial clock (CLK) input pin.
Serial Data Output (SO)
The SPI Serial Data Output pin provides a means for status and data to be serially read out (shifted out of) the
device. Data is shifted out on the falling edge of the serial clock (CLK) input pin.
Serial Clock (CLK)
The SPI Serial Clock Input pin provides the timing for serial input and output operations.
Chip Select (CS)
The SPI Chip Select pin enables and disables SPI interface operations. When the Chip Select is high the SPI inter-
face is deselected and the Serial Data Output (SO) pin is at high impedance. When it is brought low, the SPI inter-
LatticeXP2 Memory Usage Guide
2
C TAG memory device.
10-43
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