FPGA - Field Programmable Gate Array 8K LUTs 201 I/O Inst on DSP 1.2V -5 Spd

 

LFXP2-8E-5FTN256I

Manufacturer Part NumberLFXP2-8E-5FTN256I
DescriptionFPGA - Field Programmable Gate Array 8K LUTs 201 I/O Inst on DSP 1.2V -5 Spd
ManufacturerLattice
LFXP2-8E-5FTN256I datasheets

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Specifications of LFXP2-8E-5FTN256I

Number Of Macrocells8000Number Of Programmable I/os201
Data Ram Size226304Supply Voltage (max)1.26 V
Maximum Operating Temperature+ 100 CMinimum Operating Temperature- 40 C
Mounting StyleSMD/SMTSupply Voltage (min)1.14 V
Package / CaseFTBGA-256Number Of Logic Elements/cells*
Number Of Labs/clbs*Total Ram Bits226304
Number Of I /o201Number Of Gates-
Voltage - Supply1.14 V ~ 1.26 VMounting Type*
Operating Temperature-40°C ~ 100°CPackage256FTBGA
Family NameLatticeXP2Device Logic Units8000
Typical Operating Supply Voltage1.2 VMaximum Number Of User I/os201
Ram Bits226304Re-programmability SupportYes
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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Lattice Semiconductor
Revision History
Date
February 2007
July 2007
November 2007
January 2008
February 2008
March 2008
June 2008
June 2008
November 2008
Version
01.0
Initial release.
01.1
Added FlashBak Capability section.
01.2
TAG memory added.
01.3
Updated Read_Tag Commands Waveform diagram. Changed minimum
delay between the 3rd and 24th dummy clock from 3µs to 5µs.
01.4
Updated FIFO_DC without Output Registers (Non-Pipelined) diagram.
01.5
Added FlashBAK Waveform diagram.
01.6
Removed Read-Before-Write sysMEM EBR mode.
Updated “First In First Out (FIFO, FIFO_DC) – EBR Based” section.
01.7
Added TAG memory timing waveforms and instructions.
01.8
Updated the following waveform figures: Generic Timing Diagram,
READ_ID Waveform, WRITE_EN Waveform, WRITE_DIS Waveform,
ERASE_TAT Waveform, PROGRAM_TAW Waveform, READ_TAG
Waveform, STATUS Waveform.
Updated Serial Data Input (SI) text section.
Updated Memory Modules text section.
10-53
LatticeXP2 Memory Usage Guide
Change Summary