LFXP2-8E-5FTN256I | |
|---|---|
| Manufacturer Part Number | LFXP2-8E-5FTN256I |
| Description | FPGA - Field Programmable Gate Array 8K LUTs 201 I/O Inst on DSP 1.2V -5 Spd |
| Manufacturer | Lattice |
| LFXP2-8E-5FTN256I datasheets |
|
Availability: By request
International delivery:
Warranty: 60 days
×
- We provide standard 60-days warranty for all parts. If warranty differs we always mention it beforehand. In case of return we cover shipping costs.
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Specifications of LFXP2-8E-5FTN256I | |||
|---|---|---|---|
| Number Of Macrocells | 8000 | Number Of Programmable I/os | 201 |
| Data Ram Size | 226304 | Supply Voltage (max) | 1.26 V |
| Maximum Operating Temperature | + 100 C | Minimum Operating Temperature | - 40 C |
| Mounting Style | SMD/SMT | Supply Voltage (min) | 1.14 V |
| Package / Case | FTBGA-256 | Number Of Logic Elements/cells | * |
| Number Of Labs/clbs | * | Total Ram Bits | 226304 |
| Number Of I /o | 201 | Number Of Gates | - |
| Voltage - Supply | 1.14 V ~ 1.26 V | Mounting Type | * |
| Operating Temperature | -40°C ~ 100°C | Package | 256FTBGA |
| Family Name | LatticeXP2 | Device Logic Units | 8000 |
| Typical Operating Supply Voltage | 1.2 V | Maximum Number Of User I/os | 201 |
| Ram Bits | 226304 | Re-programmability Support | Yes |
| Lead Free Status / RoHS Status | Lead free / RoHS Compliant | ||
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PrevNext
Lattice Semiconductor
Table 11-9. ODDRXC Port Names
Port Name
I/O
DA
DB
CLK
RST
Q
O
Figure 11-36 shows the Output Register Block of the LatticeXP2 device configured in ODDRXC mode.
Figure 11-36. Output Register Block in ODDRC Mode
DA
DB
ECLK
Figure 11-37 shows the timing waveform when using the ODDRXC module.
Figure 11-37. ODDRXC Waveform
XX
P0
DA
DB
XX
N0
ECLK
Reg A0
XX
Reg B0
XX
XX
Latch C0
Q
XX
ODDRX2B
This DDR output module can be used when a gearbox function is required. This primitive inputs four data streams
and muxes them together to generate a single stream of data going to the sysIO buffer.
I
Data at the negative edge of the clock
I
Data at the positive edge of the clock
I
This clock can be connected to the edge clock or to the FPGA clock
I
Reset signal
DDR data output
ODDRXC
A0
B0
C0
P1
P2
N1
N2
P0
P1
N1
N0
N0
P0
N0
P1
11-30
LatticeXP2 High-Speed I/O Interface
Definition
P3
P4
N4
N3
P2
P3
N2
N3
N3
N1
N2
N1
P2
N2
P3
N3
Q
..
..
P4
N4
P4
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