LFXP2-8E-5FTN256I | |
|---|---|
| Manufacturer Part Number | LFXP2-8E-5FTN256I |
| Description | FPGA - Field Programmable Gate Array 8K LUTs 201 I/O Inst on DSP 1.2V -5 Spd |
| Manufacturer | Lattice |
| LFXP2-8E-5FTN256I datasheets |
|
Availability: By request
International delivery:
Warranty: 60 days
×
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Specifications of LFXP2-8E-5FTN256I | |||
|---|---|---|---|
| Number Of Macrocells | 8000 | Number Of Programmable I/os | 201 |
| Data Ram Size | 226304 | Supply Voltage (max) | 1.26 V |
| Maximum Operating Temperature | + 100 C | Minimum Operating Temperature | - 40 C |
| Mounting Style | SMD/SMT | Supply Voltage (min) | 1.14 V |
| Package / Case | FTBGA-256 | Number Of Logic Elements/cells | * |
| Number Of Labs/clbs | * | Total Ram Bits | 226304 |
| Number Of I /o | 201 | Number Of Gates | - |
| Voltage - Supply | 1.14 V ~ 1.26 V | Mounting Type | * |
| Operating Temperature | -40°C ~ 100°C | Package | 256FTBGA |
| Family Name | LatticeXP2 | Device Logic Units | 8000 |
| Typical Operating Supply Voltage | 1.2 V | Maximum Number Of User I/os | 201 |
| Ram Bits | 226304 | Re-programmability Support | Yes |
| Lead Free Status / RoHS Status | Lead free / RoHS Compliant | ||
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PrevNext
Lattice Semiconductor
Configuration Tab
The Configuration Tab lists all user-accessible attributes with default values set. Upon completion, click Generate
to generate source and constraint files. The user may choose to use the .lpc file to load parameters.
Figure 11-44. Configuration Tab for DDR_Generic
The user can change the Mode parameter to choose either Input, Output, Bidirection or Tristate DDR module. The
other configuration parameters will change according to the mode selected. The Delay parameter is only available
for Input and Bidirectional modes. Similarly the Multiplier for Fixed Delay parameter is only available when the
Delay parameter is configured to Fixed.
Table 11-12. User Parameters in the IPexpress GUI
User Parameters
Mode
Mode selection for the DDR block.
Data Width
Width of the data bus.
Gearing Ratio
Gearing ratio selection.
Delay
Input delay configuration
Fixed delay setting. Available only when delay is
Multiplier for Fixed Delay
configured as fixed.
Allows for the selection of a single clock for the
Use Single Clk for 1x
gearing logic.
1. Only 1x available when Mode is Bidirection or Tristate.
DDR_MEM
Figure 11-45 shows the main window when DDR_MEM is selected. Similar to the DDR_Generic, the only entry
required here is the module name. Other entries are set to the project settings. The user may change these entries
LatticeXP2 High-Speed I/O Interface
Description
11-36
Values/Range
Default
Input, Output,
Input
Bidirectional, Tristate
1-64
8
1
1x
1x, 2x
Dynamic, Fixed,
Dynamic
Fixed XGMII
0-15
0
On/Off
Off
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