LFXP2-8E-5FTN256I | |
|---|---|
| Manufacturer Part Number | LFXP2-8E-5FTN256I |
| Description | FPGA - Field Programmable Gate Array 8K LUTs 201 I/O Inst on DSP 1.2V -5 Spd |
| Manufacturer | Lattice |
| LFXP2-8E-5FTN256I datasheets |
|
Availability: By request
International delivery:
Warranty: 60 days
×
- We provide standard 60-days warranty for all parts. If warranty differs we always mention it beforehand. In case of return we cover shipping costs.
- If you still have any questions - please contact us
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Specifications of LFXP2-8E-5FTN256I | |||
|---|---|---|---|
| Number Of Macrocells | 8000 | Number Of Programmable I/os | 201 |
| Data Ram Size | 226304 | Supply Voltage (max) | 1.26 V |
| Maximum Operating Temperature | + 100 C | Minimum Operating Temperature | - 40 C |
| Mounting Style | SMD/SMT | Supply Voltage (min) | 1.14 V |
| Package / Case | FTBGA-256 | Number Of Logic Elements/cells | * |
| Number Of Labs/clbs | * | Total Ram Bits | 226304 |
| Number Of I /o | 201 | Number Of Gates | - |
| Voltage - Supply | 1.14 V ~ 1.26 V | Mounting Type | * |
| Operating Temperature | -40°C ~ 100°C | Package | 256FTBGA |
| Family Name | LatticeXP2 | Device Logic Units | 8000 |
| Typical Operating Supply Voltage | 1.2 V | Maximum Number Of User I/os | 201 |
| Ram Bits | 226304 | Re-programmability Support | Yes |
| Lead Free Status / RoHS Status | Lead free / RoHS Compliant | ||
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PrevNext
Lattice Semiconductor
Table 11-14. User Parameters in the IPexpress GUI when in DDR2 Mode
User Parameters
I/O Standard used for the Interface. This will
I/O Buffer Configuration
also depend on the Mode selected.
Data Width
Width of the Data bus
Number of DQS will determine the number of
Number of DQS
DQS Groups
DDR Interface Frequency. This is also input to
Frequency of DQS
the DDR DLL. The values will depend on the
mode selected.
Lock/Jitter Sensitivity
DLL Sensitivity to Jitter
LSR for DDR Input Register
LSR Control
Create Clock Enable for DDR
Create Clock enable inputs to the block
Input Register
Tri-state Enable for DDR
Creates Tri-state control for the DDR data output
Output Registers
registers.
DDR Tristate enable for the
Creates Tristate control for DQS output
DQS output
DQS Buffer Configuration for
DQS Buffer can be configured as Differential
DDR2
FCRAM (“Fast Cycle Random Access Memory”) Interface
FCRAM is a DDR-type DRAM, which performs data output at both the rising and falling edges of the clock. FCRAM
devices operate at a core voltage of 2.5V with SSTL Class II I/O. It has enhanced both the core and peripheral logic
of the SDRAM. In FCRAM the address and command signals are synchronized with the clock input, and the data
pins are synchronized with the DQS signal. Data output takes place at both the rising and falling edges of the DQS.
DQS is in phase with the clock input of the device. The DDR SDRAM and DDR FCRAM controller will have differ-
ent pinouts.
LatticeXP2 devices can implement the FCRAM interface using dedicated DQS logic, input DDR registers and out-
put DDR registers, as described in the Implementing Memory Interfaces section of this document. Generation of
address and control signals for FCRAM are different than in DDR SDRAM devices. Please refer to the FCRAM
data sheets to see detailed specifications. Toshiba, Inc. and Fujitsu, Inc. offer FCRAM devices in 256Mb densities.
They are available in x8 or x16 configurations.
Board Design Guidelines
The most common challenge associated with implementing DDR memory interfaces is the board design and lay-
out. It is required that users strictly follow the guidelines recommended by memory device vendors.
Some of the common recommendations include matching trace lengths of interface signals to avoid skew, proper
DQ-DQS signal grouping, proper termination of the SSTL2 or SSTL18 I/O Standard, proper VREF and VTT gener-
ation decoupling and proper PCB routing.
The following documents include board layout guidelines:
• www.idt.com, IDT, PCB Design for Double Data Rate Memory
• www.motorola.com, AN2582, Hardware and Layout Design Considerations for DDR Interfaces
References
• www.jedec.org, JEDEC Standard 79, Double Data Rate (DDR) SDRAM Specification
• www.micron.com, DDR SDRAM Data Sheets
LatticeXP2 High-Speed I/O Interface
Description
166MHz, 200MHz, 266MHz
11-39
Values/Range
Default
SSTL18_I, SSTL18_II
SSTL18_I
8-64
8
1, 2, 4, 8
1
200MHz
High, Low
High
RESET, SET
RESET
On/Off
Off
On/Off
On
On/Off
On
On/Off
Off
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