A3PN125-ZVQG100 Actel, A3PN125-ZVQG100 Datasheet - Page 47

• Manufacturer Part Number: A3PN125-ZVQG100
• Description: FPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano
• Manufacturer: Actel

Specifications of A3PN125-ZVQG100

• Processor Series: A3PN125
• Core: IP Core
• Number Of Macrocells: 1024
• Maximum Operating Frequency: 350 MHz
• Number Of Programmable I/os: 71
• Data Ram Size: 36 Kbit
• Delay Time: 1.02 ns
• Supply Voltage (max): 3.3 V
• Supply Current: 2 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: - 20 C
• Development Tools By Supplier: AGLN-Nano-Kit, AGLN-Z-Nano-Kit, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FloasPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.5 V
• Number Of Gates: 125 K
• Package / Case: VQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-44 • Minimum and Maximum DC Input and Output Levels
Figure 2-8 • AC Loading
Table 2-45 • 1.8 V LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads
1.8 V LVCMOS
Drive Strength
2 mA
4 mA
Notes:
1. I
2. I
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
Input LOW (V)
0
Notes:
1. Measuring point = Vtrip. See
2. Capacitive Load for A3PN060, A3PN125, and A3PN250 is 35 pF.
larger when operating outside recommended ranges.
IL
IH
is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
1.8 V LVCMOS
Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general-
purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer.
Min.
–0.3 0.35 * VCCI 0.65 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI
Test Point
Datapath
V
VIL
Max.
V
Table 2-16 on page 2-17
35 pF
Input HIGH (V)
Min.
V
1.8
VIH
Enable Path
Test Point
Max.
3.6
3.6
R = 1 k
V
for a complete table of trip points.
R e v i s i o n 8
Max.
VOL
0.45
0.45
V
Measuring Point* (V)
R to VCCI for t
R to GND for t
35 pF for t
5 pF for t
VCCI – 0.45
VCCI – 0.45
0.9
VOH
Min.
V
HZ
ZH
/ t
/ t
mA mA
LZ
I
HZ
LZ
OL
2
4
ZHS
/ t
/ t
I
ZL
ZH
OH
/ t
2
4
ZL
/ t
/ t
ProASIC3 nano Flash FPGAs
ZLS
Max.
ZHS
mA
/ t
I
OSL
17
9
ZLS
3
C
LOAD
Max.
I
mA
10
OSH
11
22
(pF)
3
I
µA
IL
10
10
1
4
I
µA
IH
2- 33
10
10
2
4