FPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano

A3PN125-ZVQG100

Manufacturer Part NumberA3PN125-ZVQG100
DescriptionFPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano
ManufacturerActel
A3PN125-ZVQG100 datasheet
 

Specifications of A3PN125-ZVQG100

Processor SeriesA3PN125CoreIP Core
Number Of Macrocells1024Maximum Operating Frequency350 MHz
Number Of Programmable I/os71Data Ram Size36 Kbit
Delay Time1.02 nsSupply Voltage (max)3.3 V
Supply Current2 mAMaximum Operating Temperature+ 70 C
Minimum Operating Temperature- 20 CDevelopment Tools By SupplierAGLN-Nano-Kit, AGLN-Z-Nano-Kit, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FloasPro 4, FlashPro 3, FlashPro Lite
Mounting StyleSMD/SMTSupply Voltage (min)1.5 V
Number Of Gates125 KPackage / CaseVQFP-100
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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4 – Datasheet Information
List of Changes
The following table lists critical changes that were made in each revision of the ProASIC3 nano
datasheet.
Revision
July 2010
The versioning system for datasheets has been changed. Datasheets are
assigned a revision number that increments each time the datasheet is revised.
The
"ProASIC3 nano Device Status" table on page II
device in the device family.
Revision 8 (Apr 2010) References to differential inputs were removed from the datasheet, since
ProASIC3 nano devices do not support differential inputs (SAR 21449).
The
"ProASIC3 nano Device Status" table
The JTAG DC voltage was revised in
1, 2
Conditions
voltage (operation mode) was changed from 3.45 V to 3.6 V (SAR 25220).
The highest temperature in
for Timing Delays
The typical value for A3PN010 was revised in
Current
Characteristics. The note was revised to remove the statement that
values do not include I/O static contribution.
The following tables were updated with available information:
Table 2-8 • Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software
Settings
Table 2-9 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software
1
Settings
Table 2-10 • Different Components Contributing to Dynamic Power Consumption
in ProASIC3 nano Devices
Table 2-14 • Summary of Maximum and Minimum DC Input and Output Levels
Table 2-18 • Summary of I/O Timing Characteristics—Software Default Settings
(at 35 pF)
Table 2-19 • Summary of I/O Timing Characteristics—Software Default Settings
(at 10 pF)
Table 2-22 • I/O Weak Pull-Up/Pull-Down Resistances
range data and correct the formulas in the table notes (SAR 21348).
The text introducing
was revised to state six months at 100° instead of three months at 110° for
reliability concerns. The row for 110° was removed from the table.
Table 2-26 • I/O Input Rise Time, Fall Time, and Related I/O Reliability
revised to give values with Schmitt trigger disabled and enabled (SAR 24634).
The temperature for reliability was changed to 100ºC.
Table 2-33 • Minimum and Maximum DC Input and Output Levels for 3.3 V
LVCMOS Wide Range
Characteristics" section
tables for 3.3 V LVCMOS wide range are new.
Changes
indicates the status for each
is new.
Table 2-2 • Recommended Operating
(SAR 24052). The maximum value for VPUMP programming
Table 2-6 • Temperature and Voltage Derating Factors
was changed to 100ºC.
Table 2-7 • Quiescent Supply
Table 2-24 • Duration of Short Circuit Event before Failure
and the timing tables in the
were updated with available information. The timing
R e v i s i o n 8
Page
N/A
N/A
II
2-2
2-5
2-6
2-6
through
2-18
was revised to add wide
2-19
2-20
was
2-21
2-22
"Single-Ended I/O
4 -1