FPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano

A3PN125-ZVQG100

Manufacturer Part NumberA3PN125-ZVQG100
DescriptionFPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano
ManufacturerActel
A3PN125-ZVQG100 datasheet
 

Specifications of A3PN125-ZVQG100

Processor SeriesA3PN125CoreIP Core
Number Of Macrocells1024Maximum Operating Frequency350 MHz
Number Of Programmable I/os71Data Ram Size36 Kbit
Delay Time1.02 nsSupply Voltage (max)3.3 V
Supply Current2 mAMaximum Operating Temperature+ 70 C
Minimum Operating Temperature- 20 CDevelopment Tools By SupplierAGLN-Nano-Kit, AGLN-Z-Nano-Kit, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FloasPro 4, FlashPro 3, FlashPro Lite
Mounting StyleSMD/SMTSupply Voltage (min)1.5 V
Number Of Gates125 KPackage / CaseVQFP-100
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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Revision
Revision 1 (cont’d)
The
"I/Os Per Package"
table note 4: "For nano devices, the VQ100 package is offered in both leaded and
RoHS-compliant versions. All other packages are RoHS-compliant only."
The
"ProASIC3 nano Product Available in the Z Feature Grade" section
updated to remove QN100 for A3PN250.
The
"General Description" section
number of gates and dual-port RAM for ProASIC3 nano devices.
The device architecture figures,
Overview with Two I/O Banks (A3PN060 and A3PN125)
ProASIC3 nano Device Architecture Overview with Four I/O Banks
were revised.
Figure 1-1 • ProASIC3 Device Architecture Overview with Two I/O
Banks and No RAM (A3PN010 and A3PN030)
The
"PLL and CCC" section
A3PN020 and smaller devices.
DC and Switching
Table 2-2 • Recommended Operating Conditions
Characteristics
the VCCI row. The following table note was added: "VMV pins must be connected
Advance v0.2
to the corresponding VCCI pins."
The values in
Table 2-7 • Quiescent Supply Current Characteristics
for A3PN010, A3PN015, and A3PN020.
A table note, "All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide
range, as specified in the JESD8-B specification," was added to
Summary of Maximum and Minimum DC Input and Output
Summary of I/O Timing Characteristics—Software Default Settings (at 35
and
Table 2-19 • Summary of I/O Timing Characteristics—Software Default
Settings (at 10
3.3 V LVCMOS Wide Range was added to
Maximum Resistances
Packaging Advance
The
"48-Pin QFN"
v0.2
Note 2 for the
was added/changed to "The die attach paddle of the package is tied to ground
(GND)."
The
"100-Pin VQFP"
left corner instead of the upper right corner.
Changes
table was updated to add the following information to
was updated to give correct information about
Figure 1-3 • ProASIC3 nano Device Architecture
is new.
was revised to include information about CCC-GLs in
1, 2
was revised to add VMV to
pF).
Table 2-21 • I/O Output Buffer
1
and
Table 2-23 • I/O Short Currents I
pin diagram was revised.
"48-Pin
QFN",
"68-Pin
QFN", and
"100-Pin VQFP"
pin diagram was revised to move the pin IDs to the upper
R e v i s i o n 8
ProASIC3 nano Flash FPGAs
Page
II
was
IV
1-1
1-3
through
Figure 1-4 •
through
(A3PN250),
1-4
1-6
2-2
were revised
2-6
2-16,
2-18
Table 2-14 •
Levels,
Table 2-18 •
pF),
2-19,
2-20
/I
.
OSH
OSL
3-2
pin diagrams
3-2, 3-5,
3-9
3-9
4 -3