FPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano

A3PN125-ZVQG100

Manufacturer Part NumberA3PN125-ZVQG100
DescriptionFPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano
ManufacturerActel
A3PN125-ZVQG100 datasheet
 

Specifications of A3PN125-ZVQG100

Processor SeriesA3PN125CoreIP Core
Number Of Macrocells1024Maximum Operating Frequency350 MHz
Number Of Programmable I/os71Data Ram Size36 Kbit
Delay Time1.02 nsSupply Voltage (max)3.3 V
Supply Current2 mAMaximum Operating Temperature+ 70 C
Minimum Operating Temperature- 20 CDevelopment Tools By SupplierAGLN-Nano-Kit, AGLN-Z-Nano-Kit, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FloasPro 4, FlashPro 3, FlashPro Lite
Mounting StyleSMD/SMTSupply Voltage (min)1.5 V
Number Of Gates125 KPackage / CaseVQFP-100
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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ProASIC3 nano DC and Switching Characteristics
Power Consumption of Various Internal Resources
Table 2-10 • Different Components Contributing to Dynamic Power Consumption in ProASIC3 nano Devices
Parameter
P
Clock contribution of a Global Rib
AC1
P
Clock contribution of a Global Spine
AC2
P
Clock contribution of a VersaTile row
AC3
P
Clock contribution of a VersaTile used as a
AC4
sequential module
P
First contribution of a VersaTile used as a
AC5
sequential module
P
Second contribution of a VersaTile used as a
AC6
sequential module
P
Contribution of a VersaTile used as a
AC7
combinatorial Module
P
Average contribution of a routing net
AC8
P
Contribution of an I/O input pin
AC9
(standard-dependent)
P
Contribution of an I/O output pin
AC10
(standard-dependent)
P
Average contribution of a RAM block during a read
AC11
operation
P
Average contribution of a RAM block during a write
AC12
operation
P
Dynamic contribution for PLL
AC13
Note:
For a different output load, drive strength, or slew rate, Actel recommends using the Actel Power spreadsheet
calculator or SmartPower tool in Libero
Table 2-11 • Different Components Contributing to the Static Power Consumption in ProASIC3 nano Devices
Parameter
P
Array static power in Active mode
DC1
P
Static PLL contribution
DC4
P
Bank quiescent power (VCCI-dependent)
DC5
Notes:
1. Minimum contribution of the PLL when running at lowest frequency.
2. For a different output load, drive strength, or slew rate, Actel recommends using the Actel Power spreadsheet calculator
or SmartPower tool in Libero IDE.
2 - 8
Device Specific Dynamic Contributions
Definition
11.03
1.58
®
Integrated Design Environment (IDE) software.
Definition
1
R e vi s i o n 8
(µW/MHz)
11.03
9.3
9.3
9.3
9.3
0.81
0.81
0.4
0.4
0.4
0.81
0.12
0.07
0.29
0.29
0.70
See
Table 2-8 on page
2-6.
See
Table 2-9 on page
2-7.
25.00
N/A
30.00
N/A
2.60
N/A
Device Specific Static Power (mW)
See
Table 2-7 on page
2-6.
2.55
N/A
See
Table 2-7 on page
2-6.