FPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano

A3PN125-ZVQG100

Manufacturer Part NumberA3PN125-ZVQG100
DescriptionFPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano
ManufacturerActel
A3PN125-ZVQG100 datasheet
 

Specifications of A3PN125-ZVQG100

Processor SeriesA3PN125CoreIP Core
Number Of Macrocells1024Maximum Operating Frequency350 MHz
Number Of Programmable I/os71Data Ram Size36 Kbit
Delay Time1.02 nsSupply Voltage (max)3.3 V
Supply Current2 mAMaximum Operating Temperature+ 70 C
Minimum Operating Temperature- 20 CDevelopment Tools By SupplierAGLN-Nano-Kit, AGLN-Z-Nano-Kit, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FloasPro 4, FlashPro 3, FlashPro Lite
Mounting StyleSMD/SMTSupply Voltage (min)1.5 V
Number Of Gates125 KPackage / CaseVQFP-100
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Page 21
22
Page 22
23
Page 23
24
Page 24
25
Page 25
26
Page 26
27
Page 27
28
Page 28
29
Page 29
30
Page 30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
Page 23/106

Download datasheet (4Mb)Embed
PrevNext
Power Calculation Methodology
This section describes a simplified method to estimate power consumption of an application. For more
accurate and detailed power estimations, use the SmartPower tool in Actel Libero IDE software.
The power calculation methodology described below uses the following variables:
The number of PLLs as well as the number and the frequency of each output clock generated
The number of combinatorial and sequential cells used in the design
The internal clock frequencies
The number and the standard of I/O pins used in the design
The number of RAM blocks used in the design
Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in
page
2-11.
Enable rates of output buffers—guidelines are provided for typical applications in
page
2-11.
Read rate and write rate to the memory—guidelines are provided for typical applications in
Table 2-13 on page
2-11. The calculation should be repeated for each clock domain defined in the
design.
Methodology
Total Power Consumption—P
TOTAL
P
= P
+ P
TOTAL
STAT
DYN
P
is the total static power consumption.
STAT
P
is the total dynamic power consumption.
DYN
Total Static Power Consumption—P
P
= P
+ N
* P
+ N
STAT
DC1
INPUTS
DC2
N
is the number of I/O input buffers used in the design.
INPUTS
N
is the number of I/O output buffers used in the design.
OUTPUTS
Total Dynamic Power Consumption—P
P
= P
+ P
+ P
DYN
CLOCK
S-CELL
C-CELL
Global Clock Contribution—P
CLOCK
P
= (P
+ N
*P
+ N
CLOCK
AC1
SPINE
AC2
N
is the number of global spines used in the user design—guidelines are provided in
SPINE
on page
2-11.
N
is the number of VersaTile rows used in the design—guidelines are provided in
ROW
page
2-11.
F
is the global clock signal frequency.
CLK
N
is the number of VersaTiles used as sequential modules in the design.
S-CELL
P
, P
, P
, and P
are device-dependent.
AC1
AC2
AC3
AC4
Sequential Cells Contribution—P
α
P
= N
* (P
+
/ 2 * P
S-CELL
S-CELL
AC5
1
N
is the number of VersaTiles used as sequential modules in the design. When a multi-tile
S-CELL
sequential cell is used, it should be accounted for as 1.
α
is the toggle rate of VersaTile outputs—guidelines are provided in
1
F
is the global clock signal frequency.
CLK
STAT
* P
OUTPUTS
DC3
DYN
+ P
+ P
+ P
+ P
NET
INPUTS
OUTPUTS
MEMORY
*P
+ N
* P
) * F
ROW
AC3
S-CELL
AC4
CLK
S-CELL
) * F
AC6
CLK
Table 2-12 on page
R e v i s i o n 8
ProASIC3 nano Flash FPGAs
Table 2-12 on
Table 2-13 on
+ P
PLL
Table 2-12
Table 2-12 on
2-11.
2 -9