A3PN125-ZVQG100 Actel, A3PN125-ZVQG100 Datasheet - Page 26

FPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano

A3PN125-ZVQG100

Manufacturer Part Number
A3PN125-ZVQG100
Description
FPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano
Manufacturer
Actel
Datasheet

Specifications of A3PN125-ZVQG100

Processor Series
A3PN125
Core
IP Core
Number Of Macrocells
1024
Maximum Operating Frequency
350 MHz
Number Of Programmable I/os
71
Data Ram Size
36 Kbit
Delay Time
1.02 ns
Supply Voltage (max)
3.3 V
Supply Current
2 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
- 20 C
Development Tools By Supplier
AGLN-Nano-Kit, AGLN-Z-Nano-Kit, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FloasPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.5 V
Number Of Gates
125 K
Package / Case
VQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
ProASIC3 nano DC and Switching Characteristics
User I/O Characteristics
Timing Model
I/O Module
(Registered)
t
= 1.04 ns
PY
Input LVCMOS 2.5 V
D
Q
t
= 0.24 ns
ICLKQ
t
= 0.26 ns
ISUD
Input LVTTL
Clock
t
= 0.84 ns
PY
I/O Module
(Non-Registered)
LVCMOS 1.5 V
t
= 1.14 ns
PY
Figure 2-2 • Timing Model
Operating Conditions: –2 Speed, Commercial Temperature Range (T
VCC = 1.425 V, with Default Loading at 10 pF
2- 12
(Non-Registered)
Combinational Cell
Combinational Cell
Y
Y
t
= 0.56 ns
t
= 0.49 ns
PD
PD
I/O Module
(Non-Registered)
Combinational Cell
Y
t
= 2.87 ns
t
= 0.87 ns
DP
PD
I/O Module
Combinational Cell
(Non-Registered)
Y
t
= 2.21 ns
DP
t
= 0.51 ns
PD
I/O Module
(Non-Registered)
Combinational Cell
Y
t
= 3.02 ns
t
= 0.47 ns
DP
PD
Register Cell
Register Cell
Combinational Cell
Y
D
Q
D
Q
t
= 0.47 ns
PD
t
= 0.55 ns
t
= 0.55 ns
CLKQ
CLKQ
t
= 0.43 ns
t
= 0.43 ns
SUD
SUD
Input LVTTL
Input LVTTL
Clock
Clock
t
= 0.84 ns
t
= 0.84 ns
PY
PY
R e visio n 8
I/O Module
LVCMOS 2.5V Output Drive
Strength = 8 mA High Slew Rate
t
= 2.25 ns
DP
LVTTL Output drive strength = 4 mA
High slew rate
LVTTL Output drive strength = 8 mA
High slew rate
LVCMOS 1.5 V Output drive strength = 2 mA
High slew rate
I/O Module
(Registered)
D
Q
LVTTL 3.3 V Output drive
strength = 8 mA High slew rate
t
= 2.21 ns
DP
t
= 0.59 ns
OCLKQ
t
= 0.31 ns
OSUD
= 70°C), Worst Case
J

Related parts for A3PN125-ZVQG100