FPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano

A3PN125-ZVQG100

Manufacturer Part NumberA3PN125-ZVQG100
DescriptionFPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano
ManufacturerActel
A3PN125-ZVQG100 datasheet
 

Specifications of A3PN125-ZVQG100

Processor SeriesA3PN125CoreIP Core
Number Of Macrocells1024Maximum Operating Frequency350 MHz
Number Of Programmable I/os71Data Ram Size36 Kbit
Delay Time1.02 nsSupply Voltage (max)3.3 V
Supply Current2 mAMaximum Operating Temperature+ 70 C
Minimum Operating Temperature- 20 CDevelopment Tools By SupplierAGLN-Nano-Kit, AGLN-Z-Nano-Kit, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FloasPro 4, FlashPro 3, FlashPro Lite
Mounting StyleSMD/SMTSupply Voltage (min)1.5 V
Number Of Gates125 KPackage / CaseVQFP-100
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
Page 51
52
Page 52
53
Page 53
54
Page 54
55
Page 55
56
Page 56
57
Page 57
58
Page 58
59
Page 59
60
Page 60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
Page 53/106

Download datasheet (4Mb)Embed
PrevNext
Table 2-56 • Parameter Definition and Measuring Nodes
Parameter Name
t
Clock-to-Q of the Output Data Register
OCLKQ
t
Data Setup Time for the Output Data Register
OSUD
t
Data Hold Time for the Output Data Register
OHD
t
Enable Setup Time for the Output Data Register
OSUE
t
Enable Hold Time for the Output Data Register
OHE
t
Asynchronous Preset-to-Q of the Output Data Register
OPRE2Q
t
Asynchronous Preset Removal Time for the Output Data Register
OREMPRE
t
Asynchronous Preset Recovery Time for the Output Data Register
ORECPRE
t
Clock-to-Q of the Output Enable Register
OECLKQ
t
Data Setup Time for the Output Enable Register
OESUD
t
Data Hold Time for the Output Enable Register
OEHD
t
Enable Setup Time for the Output Enable Register
OESUE
t
Enable Hold Time for the Output Enable Register
OEHE
t
Asynchronous Preset-to-Q of the Output Enable Register
OEPRE2Q
t
Asynchronous Preset Removal Time for the Output Enable Register
OEREMPRE
t
Asynchronous Preset Recovery Time for the Output Enable Register
OERECPRE
t
Clock-to-Q of the Input Data Register
ICLKQ
t
Data Setup Time for the Input Data Register
ISUD
t
Data Hold Time for the Input Data Register
IHD
t
Enable Setup Time for the Input Data Register
ISUE
t
Enable Hold Time for the Input Data Register
IHE
t
Asynchronous Preset-to-Q of the Input Data Register
IPRE2Q
t
Asynchronous Preset Removal Time for the Input Data Register
IREMPRE
t
Asynchronous Preset Recovery Time for the Input Data Register
IRECPRE
*
See
Figure 2-10 on page 2-38
for more information.
Parameter Definition
R e v i s i o n 8
ProASIC3 nano Flash FPGAs
Measuring Nodes
(from, to)*
H, DOUT
F, H
F, H
G, H
G, H
L, DOUT
L, H
L, H
H, EOUT
J, H
J, H
K, H
K, H
I, EOUT
I, H
I, H
A, E
C, A
C, A
B, A
B, A
D, E
D, A
D, A
2- 39