FPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano

A3PN125-ZVQG100

Manufacturer Part NumberA3PN125-ZVQG100
DescriptionFPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano
ManufacturerActel
A3PN125-ZVQG100 datasheet
 

Specifications of A3PN125-ZVQG100

Processor SeriesA3PN125CoreIP Core
Number Of Macrocells1024Maximum Operating Frequency350 MHz
Number Of Programmable I/os71Data Ram Size36 Kbit
Delay Time1.02 nsSupply Voltage (max)3.3 V
Supply Current2 mAMaximum Operating Temperature+ 70 C
Minimum Operating Temperature- 20 CDevelopment Tools By SupplierAGLN-Nano-Kit, AGLN-Z-Nano-Kit, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FloasPro 4, FlashPro 3, FlashPro Lite
Mounting StyleSMD/SMTSupply Voltage (min)1.5 V
Number Of Gates125 KPackage / CaseVQFP-100
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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Table 2-57 • Parameter Definition and Measuring Nodes
Parameter Name
t
Clock-to-Q of the Output Data Register
OCLKQ
t
Data Setup Time for the Output Data Register
OSUD
t
Data Hold Time for the Output Data Register
OHD
t
Enable Setup Time for the Output Data Register
OSUE
t
Enable Hold Time for the Output Data Register
OHE
t
Asynchronous Clear-to-Q of the Output Data Register
OCLR2Q
t
Asynchronous Clear Removal Time for the Output Data Register
OREMCLR
t
Asynchronous Clear Recovery Time for the Output Data Register
ORECCLR
t
Clock-to-Q of the Output Enable Register
OECLKQ
t
Data Setup Time for the Output Enable Register
OESUD
t
Data Hold Time for the Output Enable Register
OEHD
t
Enable Setup Time for the Output Enable Register
OESUE
t
Enable Hold Time for the Output Enable Register
OEHE
t
Asynchronous Clear-to-Q of the Output Enable Register
OECLR2Q
t
Asynchronous Clear Removal Time for the Output Enable Register
OEREMCLR
t
Asynchronous Clear Recovery Time for the Output Enable Register
OERECCLR
t
Clock-to-Q of the Input Data Register
ICLKQ
t
Data Setup Time for the Input Data Register
ISUD
t
Data Hold Time for the Input Data Register
IHD
t
Enable Setup Time for the Input Data Register
ISUE
t
Enable Hold Time for the Input Data Register
IHE
t
Asynchronous Clear-to-Q of the Input Data Register
ICLR2Q
t
Asynchronous Clear Removal Time for the Input Data Register
IREMCLR
t
Asynchronous Clear Recovery Time for the Input Data Register
IRECCLR
*
See
Figure 2-11 on page 2-40
for more information.
Parameter Definition
R e v i s i o n 8
ProASIC3 nano Flash FPGAs
Measuring Nodes
(from, to)*
HH, DOUT
FF, HH
FF, HH
GG, HH
GG, HH
LL, DOUT
LL, HH
LL, HH
HH, EOUT
JJ, HH
JJ, HH
KK, HH
KK, HH
II, EOUT
II, HH
II, HH
AA, EE
CC, AA
CC, AA
BB, AA
BB, AA
DD, EE
DD, AA
DD, AA
2- 41