FPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano

A3PN125-ZVQG100

Manufacturer Part NumberA3PN125-ZVQG100
DescriptionFPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano
ManufacturerActel
A3PN125-ZVQG100 datasheet
 

Specifications of A3PN125-ZVQG100

Processor SeriesA3PN125CoreIP Core
Number Of Macrocells1024Maximum Operating Frequency350 MHz
Number Of Programmable I/os71Data Ram Size36 Kbit
Delay Time1.02 nsSupply Voltage (max)3.3 V
Supply Current2 mAMaximum Operating Temperature+ 70 C
Minimum Operating Temperature- 20 CDevelopment Tools By SupplierAGLN-Nano-Kit, AGLN-Z-Nano-Kit, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FloasPro 4, FlashPro 3, FlashPro Lite
Mounting StyleSMD/SMTSupply Voltage (min)1.5 V
Number Of Gates125 KPackage / CaseVQFP-100
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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Output Register
50%
50%
CLK
t
50%
1
Data_out
Enable
50%
t
OHE
t
Preset
OSUE
Clear
DOUT
Figure 2-13 • Output Register Timing Diagram
Timing Characteristics
Table 2-59 • Output Data Register Propagation Delays
Commercial-Case Conditions: T
Parameter
t
Clock-to-Q of the Output Data Register
OCLKQ
t
Data Setup Time for the Output Data Register
OSUD
t
Data Hold Time for the Output Data Register
OHD
t
Asynchronous Clear-to-Q of the Output Data Register
OCLR2Q
t
Asynchronous Preset-to-Q of the Output Data Register
OPRE2Q
t
Asynchronous Clear Removal Time for the Output Data Register
OREMCLR
t
Asynchronous Clear Recovery Time for the Output Data Register
ORECCLR
t
Asynchronous Preset Removal Time for the Output Data Register
OREMPRE
t
Asynchronous Preset Recovery Time for the Output Data Register
ORECPRE
t
Asynchronous Clear Minimum Pulse Width for the Output Data Register
OWCLR
t
Asynchronous Preset Minimum Pulse Width for the Output Data Register
OWPRE
t
Clock Minimum Pulse Width HIGH for the Output Data Register
OCKMPWH
t
Clock Minimum Pulse Width LOW for the Output Data Register
OCKMPWL
Note:
For specific junction temperature and voltage supply levels, refer to
50%
50%
t
OSUD
OHD
0
50%
t
t
OWPRE
ORECPRE
50%
50%
t
t
ORECCLR
OWCLR
50%
50%
t
OPRE2Q
50%
50%
50%
t
OCLR2Q
t
OCLKQ
= 70°C, Worst-Case VCC = 1.425 V
J
Description
Table 2-6 on page 2-5
R e v i s i o n 8
ProASIC3 nano Flash FPGAs
t
t
OCKMPWH
OCKMPWL
50%
50%
50%
t
OREMPRE
50%
t
OREMCLR
50%
–2
–1
Std. Units
0.59 0.67 0.79
ns
0.31 0.36 0.42
ns
0.00 0.00 0.00
ns
0.80 0.91 1.07
ns
0.80 0.91 1.07
ns
0.00 0.00 0.00
ns
0.22 0.25 0.30
ns
0.00 0.00 0.00
ns
0.22 0.25 0.30
ns
0.22 0.25 0.30
ns
0.22 0.25 0.30
ns
0.36 0.41 0.48
ns
0.32 0.37 0.43
ns
for derating values.
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