FPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano

A3PN125-ZVQG100

Manufacturer Part NumberA3PN125-ZVQG100
DescriptionFPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano
ManufacturerActel
A3PN125-ZVQG100 datasheet
 

Specifications of A3PN125-ZVQG100

Processor SeriesA3PN125CoreIP Core
Number Of Macrocells1024Maximum Operating Frequency350 MHz
Number Of Programmable I/os71Data Ram Size36 Kbit
Delay Time1.02 nsSupply Voltage (max)3.3 V
Supply Current2 mAMaximum Operating Temperature+ 70 C
Minimum Operating Temperature- 20 CDevelopment Tools By SupplierAGLN-Nano-Kit, AGLN-Z-Nano-Kit, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FloasPro 4, FlashPro 3, FlashPro Lite
Mounting StyleSMD/SMTSupply Voltage (min)1.5 V
Number Of Gates125 KPackage / CaseVQFP-100
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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ProASIC3 nano DC and Switching Characteristics
Output Enable Register
50%
CLK
50%
1
D_Enable
50%
Enable
t
t
OESUE
OEHE
Preset
Clear
EOUT
Figure 2-14 • Output Enable Register Timing Diagram
Timing Characteristics
Table 2-60 • Output Enable Register Propagation Delays
Commercial-Case Conditions: T
Parameter
t
Clock-to-Q of the Output Enable Register
OECLKQ
t
Data Setup Time for the Output Enable Register
OESUD
t
Data Hold Time for the Output Enable Register
OEHD
t
Asynchronous Clear-to-Q of the Output Enable Register
OECLR2Q
t
Asynchronous Preset-to-Q of the Output Enable Register
OEPRE2Q
t
Asynchronous Clear Removal Time for the Output Enable Register
OEREMCLR
t
Asynchronous Clear Recovery Time for the Output Enable Register
OERECCLR
t
Asynchronous Preset Removal Time for the Output Enable Register
OEREMPRE
t
Asynchronous Preset Recovery Time for the Output Enable Register
OERECPRE
t
Asynchronous Clear Minimum Pulse Width for the Output Enable Register
OEWCLR
t
Asynchronous Preset Minimum Pulse Width for the Output Enable Register
OEWPRE
t
Clock Minimum Pulse Width HIGH for the Output Enable Register
OECKMPWH
t
Clock Minimum Pulse Width LOW for the Output Enable Register
OECKMPWL
Note:
For specific junction temperature and voltage supply levels, refer to
2- 44
50%
50%
50%
t
t
OESUD
OEHD
50%
0
t
OEWPRE
t
OERECPRE
50%
50%
t
OEWCLR
50%
t
t
OECLR2Q
OEPRE2Q
50%
50%
50%
t
OECLKQ
= 70°C, Worst-Case VCC = 1.425 V
J
Description
R e visio n 8
t
t
OECKMPWH
OECKMPWL
50%
50%
50%
t
OEREMPRE
50%
t
t
OEREMCLR
OERECCLR
50%
50%
–2
–1
Std. Units
0.44 0.51 0.59
0.31 0.36 0.42
0.00 0.00 0.00
0.67 0.76 0.89
0.67 0.76 0.89
0.00 0.00 0.00
0.22 0.25 0.30
0.00 0.00 0.00
0.22 0.25 0.30
0.22 0.25 0.30
0.22 0.25 0.30
0.36 0.41 0.48
0.32 0.37 0.43
Table 2-6 on page 2-5
for derating values.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns