FPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano

A3PN125-ZVQG100

Manufacturer Part NumberA3PN125-ZVQG100
DescriptionFPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano
ManufacturerActel
A3PN125-ZVQG100 datasheet
 

Specifications of A3PN125-ZVQG100

Processor SeriesA3PN125CoreIP Core
Number Of Macrocells1024Maximum Operating Frequency350 MHz
Number Of Programmable I/os71Data Ram Size36 Kbit
Delay Time1.02 nsSupply Voltage (max)3.3 V
Supply Current2 mAMaximum Operating Temperature+ 70 C
Minimum Operating Temperature- 20 CDevelopment Tools By SupplierAGLN-Nano-Kit, AGLN-Z-Nano-Kit, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FloasPro 4, FlashPro 3, FlashPro Lite
Mounting StyleSMD/SMTSupply Voltage (min)1.5 V
Number Of Gates125 KPackage / CaseVQFP-100
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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Output DDR Module
A
Data_F
(from core)
B
CLK
CLKBUF
C
D
Data_R
(from core)
B
CLR
INBUF
C
Figure 2-17 • Output DDR Timing Model
Table 2-63 • Parameter Definitions
Parameter Name
Parameter Definition
t
Clock-to-Out
DDROCLKQ
t
Asynchronous Clear-to-Out
DDROCLR2Q
t
Clear Removal
DDROREMCLR
t
Clear Recovery
DDRORECCLR
t
Data Setup Data_F
DDROSUD1
t
Data Setup Data_R
DDROSUD2
t
Data Hold Data_F
DDROHD1
t
Data Hold Data_R
DDROHD2
ProASIC3 nano Flash FPGAs
Output DDR
X
FF1
0
X
E
X
1
X
FF2
X
X
DDR_OUT
Measuring Nodes (from, to)
R e v i s i o n 8
Out
X
OUTBUF
B, E
C, E
C, B
C, B
A, B
D, B
A, B
D, B
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