FPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano

A3PN125-ZVQG100

Manufacturer Part NumberA3PN125-ZVQG100
DescriptionFPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano
ManufacturerActel
A3PN125-ZVQG100 datasheet
 

Specifications of A3PN125-ZVQG100

Processor SeriesA3PN125CoreIP Core
Number Of Macrocells1024Maximum Operating Frequency350 MHz
Number Of Programmable I/os71Data Ram Size36 Kbit
Delay Time1.02 nsSupply Voltage (max)3.3 V
Supply Current2 mAMaximum Operating Temperature+ 70 C
Minimum Operating Temperature- 20 CDevelopment Tools By SupplierAGLN-Nano-Kit, AGLN-Z-Nano-Kit, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FloasPro 4, FlashPro 3, FlashPro Lite
Mounting StyleSMD/SMTSupply Voltage (min)1.5 V
Number Of Gates125 KPackage / CaseVQFP-100
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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ProASIC3 nano DC and Switching Characteristics
CLK
Data_F
1
2
t
DDROREMCLR
Data_R
6
7
t
CLR
DDROREMCLR
t
DDROCLR2Q
Out
Figure 2-18 • Output DDR Timing Diagram
Timing Characteristics
Table 2-64 • Output DDR Propagation Delays
Commercial-Case Conditions: T
Parameter
t
Clock-to-Out of DDR for Output DDR
DDROCLKQ
t
Data_F Data Setup for Output DDR
DDROSUD1
t
Data_R Data Setup for Output DDR
DDROSUD2
t
Data_F Data Hold for Output DDR
DDROHD1
t
Data_R Data Hold for Output DDR
DDROHD2
t
Asynchronous Clear-to-Out for Output DDR
DDROCLR2Q
t
Asynchronous Clear Removal Time for Output DDR
DDROREMCLR
t
Asynchronous Clear Recovery Time for Output DDR
DDRORECCLR
t
Asynchronous Clear Minimum Pulse Width for Output DDR
DDROWCLR1
t
Clock Minimum Pulse Width HIGH for the Output DDR
DDROCKMPWH
t
Clock Minimum Pulse Width LOW for the Output DDR
DDROCKMPWL
F
Maximum Frequency for the Output DDR
DDOMAX
Note:
For specific junction temperature and voltage supply levels, refer to
2- 48
t
t
DDROHD2
DDROSUD2
4
3
t
DDROHD1
8
9
t
DDROCLKQ
7
2
8
3
= 70°C, Worst-Case VCC = 1.425 V
J
Description
Table 2-6 on page 2-5
R e visio n 8
5
10
11
t
DDRORECCLR
9
4
10
–2
–1
Std.
Units
0.70
0.80
0.94
ns
0.38
0.43
0.51
ns
0.38
0.43
0.51
ns
0.00
0.00
0.00
ns
0.00
0.00
0.00
ns
0.80
0.91
1.07
ns
0.00
0.00
0.00
ns
0.22
0.25
0.30
ns
0.22
0.25
0.30
ns
0.36
0.41
0.48
ns
0.32
0.37
0.43
ns
350.00 350.00 350.00
MHz
for derating values.

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