FPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano

A3PN125-ZVQG100

Manufacturer Part NumberA3PN125-ZVQG100
DescriptionFPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano
ManufacturerActel
A3PN125-ZVQG100 datasheet
 

Specifications of A3PN125-ZVQG100

Processor SeriesA3PN125CoreIP Core
Number Of Macrocells1024Maximum Operating Frequency350 MHz
Number Of Programmable I/os71Data Ram Size36 Kbit
Delay Time1.02 nsSupply Voltage (max)3.3 V
Supply Current2 mAMaximum Operating Temperature+ 70 C
Minimum Operating Temperature- 20 CDevelopment Tools By SupplierAGLN-Nano-Kit, AGLN-Z-Nano-Kit, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FloasPro 4, FlashPro 3, FlashPro Lite
Mounting StyleSMD/SMTSupply Voltage (min)1.5 V
Number Of Gates125 KPackage / CaseVQFP-100
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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Page 70/106

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ProASIC3 nano DC and Switching Characteristics
Table 2-71 • A3PN125 Global Resource
Commercial-Case Conditions: T
Parameter Description
t
Input LOW Delay for Global Clock
RCKL
t
Input HIGH Delay for Global Clock
RCKH
t
Minimum Pulse Width HIGH for Global Clock
RCKMPWH
t
Minimum Pulse Width LOW for Global Clock
RCKMPWL
t
Maximum Skew for Global Clock
RCKSW
F
Maximum Frequency for Global Clock
RMAX
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage-supply levels, refer to
Table 2-72 • A3PN250 Global Resource
Commercial-Case Conditions: T
Parameter Description
t
Input LOW Delay for Global Clock
RCKL
t
Input HIGH Delay for Global Clock
RCKH
t
Minimum Pulse Width HIGH for Global Clock
RCKMPWH
t
Minimum Pulse Width LOW for Global Clock
RCKMPWL
t
Maximum Skew for Global Clock
RCKSW
F
Maximum Frequency for Global Clock
RMAX
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage-supply levels, refer to
2- 56
= 70°C, VCC = 1.425 V
J
–2
1
2
Min.
Max.
Min.
0.76
0.99
0.87
0.76
1.02
0.87
0.26
Table 2-6 on page 2-5
= 70°C, VCC = 1.425 V
J
–2
1
2
Min.
Max.
Min.
0.79
1.02
0.90
0.78
1.04
0.88
0.26
Table 2-6 on page 2-5
R e visio n 8
–1
Std.
1
2
1
2
Max.
Min.
Max.
Units
1.12
1.02
1.32
ns
1.17
1.02
1.37
ns
ns
ns
0.30
0.35
ns
MHz
for derating values.
–1
Std.
1
2
1
2
Max.
Min.
Max.
Units
1.16
1.06
1.36
ns
1.18
1.04
1.39
ns
ns
ns
0.30
0.35
ns
MHz
for derating values.